SDC2921AZ-E1 データシートの表示（PDF） - Unspecified

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SDC2921AZ-E1

Voltage Mode PWM Controller

Unspecified 

Voltage Mode PWM Controller

Datasheet

SDC2921

Under Voltage Protection Delay Time

REM

NT REMON

ME tUVP

U UVP

C Figure 6. Delay Time

O Pulse Width Modulation Block

D The output pulse width modulation is generated by decrease of the output pulse width. Also, the SS(Soft-Start)

comparison of the sawtooth waveform from the capacitor limits the output pulse width. The timing diagram is

L CT to the feedback of the voltage. Therefore, an increase shown as below:

IA in feedback control signal amplitude cause a linear

ENT CT

DTC

ID FF-CLK

NF FF-Q

CO FF-QN

PWM OUT

C1

SDCC2

Figure 7. PWM Block

The function of PT

This signal is prepared for extra OVP/OPP (VPT > 1.25V) or disable under voltage protection function (VPT < 0.62V)

December, 2013 Rev. 1.2

©2013 Shaoxing Devechip Microelectronics Co., Ltd.

10/13

www.sdc-semi.com

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