82801IBICH9 データシートの表示（PDF） - Intel

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82801IBICH9

Intel® I/O Controller Hub 9 (ICH9) Family

Intel 

5.6

5.7

5.8

5.9

5.10

LPC DMA ........................................................................................................ 131

5.6.1 Asserting DMA Requests........................................................................ 131

5.6.2 Abandoning DMA Requests .................................................................... 132

5.6.3 General Flow of DMA Transfers............................................................... 132

5.6.4 Terminal Count .................................................................................... 133

5.6.5 Verify Mode ......................................................................................... 133

5.6.6 DMA Request Deassertion...................................................................... 133

5.6.7 SYNC Field / LDRQ# Rules ..................................................................... 134

8254 Timers (D31:F0) ..................................................................................... 135

5.7.1 Timer Programming .............................................................................. 135

5.7.2 Reading from the Interval Timer............................................................. 136

5.7.2.1 Simple Read........................................................................... 136

5.7.2.2 Counter Latch Command.......................................................... 137

5.7.2.3 Read Back Command .............................................................. 137

8259 Interrupt Controllers (PIC) (D31:F0) .......................................................... 138

5.8.1 Interrupt Handling ................................................................................ 139

5.8.1.1 Generating Interrupts.............................................................. 139

5.8.1.2 Acknowledging Interrupts ........................................................ 139

5.8.1.3 Hardware/Software Interrupt Sequence ..................................... 140

5.8.2 Initialization Command Words (ICWx) ..................................................... 140

5.8.2.1 ICW1 .................................................................................... 140

5.8.2.2 ICW2 .................................................................................... 141

5.8.2.3 ICW3 .................................................................................... 141

5.8.2.4 ICW4 .................................................................................... 141

5.8.3 Operation Command Words (OCW) ......................................................... 141

5.8.4 Modes of Operation .............................................................................. 141

5.8.4.1 Fully Nested Mode................................................................... 141

5.8.4.2 Special Fully-Nested Mode........................................................ 142

5.8.4.3 Automatic Rotation Mode (Equal Priority Devices)........................ 142

5.8.4.4 Specific Rotation Mode (Specific Priority).................................... 142

5.8.4.5 Poll Mode ............................................................................... 142

5.8.4.6 Cascade Mode ........................................................................ 143

5.8.4.7 Edge and Level Triggered Mode ................................................ 143

5.8.4.8 End of Interrupt (EOI) Operations ............................................. 143

5.8.4.9 Normal End of Interrupt........................................................... 143

5.8.4.10 Automatic End of Interrupt Mode .............................................. 143

5.8.5 Masking Interrupts ............................................................................... 144

5.8.5.1 Masking on an Individual Interrupt Request ................................ 144

5.8.5.2 Special Mask Mode .................................................................. 144

5.8.6 Steering PCI Interrupts ......................................................................... 144

Advanced Programmable Interrupt Controller (APIC) (D31:F0) .............................. 145

5.9.1 Interrupt Handling ................................................................................ 145

5.9.2 Interrupt Mapping ................................................................................ 145

5.9.3 PCI / PCI Express* Message-Based Interrupts .......................................... 146

5.9.4 Front Side Bus Interrupt Delivery ........................................................... 146

5.9.4.1 Edge-Triggered Operation ........................................................ 147

5.9.4.2 Level-Triggered Operation........................................................ 147

5.9.4.3 Registers Associated with Front Side Bus Interrupt Delivery .......... 147

5.9.4.4 Interrupt Message Format........................................................ 147

5.9.5 IOxAPIC Address Remapping ................................................................. 148

5.9.6 External Interrupt Controller Support ...................................................... 148

Serial Interrupt (D31:F0) ................................................................................. 149

5.10.1 Start Frame ......................................................................................... 149

5.10.2 Data Frames........................................................................................ 150

5.10.3 Stop Frame ......................................................................................... 150

5.10.4 Specific Interrupts Not Supported via SERIRQ .......................................... 150

Intel® I/O Controller Hub 9 (ICH9) Family Datasheet

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