82801IBICH9 データシートの表示（PDF） - Intel

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82801IBICH9

Intel® I/O Controller Hub 9 (ICH9) Family

Intel 

5.17

5.18

5.19

5.16.10 AHCI Operation .................................................................................... 201

5.16.11 Serial ATA Reference Clock Low Power Request (SATACLKREQ#) ................ 201

5.16.12 SGPIO Signals ...................................................................................... 201

5.16.12.1Mechanism ............................................................................. 202

5.16.12.2Message Format...................................................................... 202

5.16.12.3LED Message Type .................................................................. 203

5.16.12.4SGPIO Waveform .................................................................... 205

5.16.13 External SATA ...................................................................................... 206

High Precision Event Timers .............................................................................. 206

5.17.1 Timer Accuracy .................................................................................... 206

5.17.2 Interrupt Mapping................................................................................. 206

5.17.3 Periodic vs. Non-Periodic Modes .............................................................. 207

5.17.4 Enabling the Timers .............................................................................. 208

5.17.5 Interrupt Levels.................................................................................... 208

5.17.6 Handling Interrupts ............................................................................... 208

5.17.7 Issues Related to 64-Bit Timers with 32-Bit Processors .............................. 209

USB UHCI Host Controllers (D29:F0, F1, F2, F3 and D26:F0, F1 and F2) ................. 209

5.18.1 Data Structures in Main Memory ............................................................. 209

5.18.2 Data Transfers to/from Main Memory ...................................................... 209

5.18.3 Data Encoding and Bit Stuffing ............................................................... 210

5.18.4 Bus Protocol......................................................................................... 210

5.18.4.1 Bit Ordering............................................................................ 210

5.18.4.2 SYNC Field ............................................................................. 210

5.18.4.3 Packet Field Formats................................................................ 210

5.18.4.4 Address Fields......................................................................... 210

5.18.4.5 Frame Number Field ................................................................ 210

5.18.4.6 Data Field .............................................................................. 210

5.18.4.7 Cyclic Redundancy Check (CRC) ................................................ 210

5.18.5 Packet Formats .................................................................................... 210

5.18.6 USB Interrupts ..................................................................................... 211

5.18.6.1 Transaction-Based Interrupts .................................................... 211

5.18.6.2 Non-Transaction Based Interrupts ............................................. 213

5.18.7 USB Power Management ........................................................................ 213

5.18.8 USB Legacy Keyboard Operation ............................................................. 214

5.18.9 Function Level Reset Support (FLR) ......................................................... 216

5.18.9.1 FLR Steps............................................................................... 216

USB EHCI Host Controllers (D29:F7 and D26:F7) ................................................. 217

5.19.1 EHC Initialization .................................................................................. 217

5.19.1.1 BIOS Initialization ................................................................... 217

5.19.1.2 Driver Initialization .................................................................. 217

5.19.1.3 EHC Resets ............................................................................ 218

5.19.2 Data Structures in Main Memory ............................................................. 218

5.19.3 USB 2.0 Enhanced Host Controller DMA ................................................... 218

5.19.4 Data Encoding and Bit Stuffing ............................................................... 218

5.19.5 Packet Formats .................................................................................... 219

5.19.6 USB 2.0 Interrupts and Error Conditions .................................................. 219

5.19.6.1 Aborts on USB 2.0-Initiated Memory Reads................................. 219

5.19.7 USB 2.0 Power Management .................................................................. 220

5.19.7.1 Pause Feature ......................................................................... 220

5.19.7.2 Suspend Feature ..................................................................... 220

5.19.7.3 ACPI Device States .................................................................. 220

5.19.7.4 ACPI System States................................................................. 221

5.19.7.5 Mobile Considerations .............................................................. 221

5.19.8 Interaction with UHCI Host Controllers..................................................... 221

5.19.8.1 Port-Routing Logic ................................................................... 222

5.19.8.2 Device Connects ..................................................................... 223

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Intel® I/O Controller Hub 9 (ICH9) Family Datasheet

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