SST39LF010-70-4I-NHE-T データシートの表示（PDF） - Microchip Technology
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SST39LF010-70-4I-NHE-T Datasheet PDF : 28 Pages
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1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash
SST39LF010 / SST39LF020 / SST39LF040
SST39VF010 / SST39VF020 / SST39VF040
Data Sheet
SST39LF/VF040 SST39LF/VF020 SST39LF/VF010
A11
A11
A11
1
32
A9
A9
A9
2
31
A8
A8
A8
3
30
A13
A13
A13
4
29
A14
A14
A14
5
28
A17
A17
NC
6
Standard Pinout
27
WE#
WE#
WE#
7
26
VDD
VDD
VDD
8
Top View
25
A18
NC
NC
9
A16
A16
A16
10
Die Up
24
23
A15
A15
A15
11
22
A12
A12
A12
12
21
A7
A7
A7
13
20
A6
A6
A6
14
19
A5
A5
A5
15
18
A4
A4
A4
16
17
1150 32-tsop WH P1.1
Figure 3: Pin Assignments for 32-lead TSOP (8mm x 14mm)
SST39LF/VF010 SST39LF/VF020 SST39LF/VF040
OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
VSS
DQ2
DQ1
DQ0
A0
A1
A2
A3
OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
VSS
DQ2
DQ1
DQ0
A0
A1
A2
A3
OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
VSS
DQ2
DQ1
DQ0
A0
A1
A2
A3
Table 1: Pin Description
Symbol Pin Name
Functions
AMS1-A0 Address Inputs To provide memory addresses. During Sector-Erase AMS-A12 address lines will
select the sector. During Block-Erase AMS-A16 address lines will select the block.
DQ7-DQ0 Data Input/output To output data during Read cycles and receive input data during Write cycles.
Data is internally latched during a Write cycle.
The outputs are in tri-state when OE# or CE# is high.
CE#
Chip Enable
To activate the device when CE# is low.
OE#
Output Enable To gate the data output buffers.
WE#
Write Enable
To control the Write operations.
VDD
Power Supply To provide power supply voltage: 3.0-3.6V for SST39LF010/020/040
2.7-3.6V for SST39VF010/020/040
VSS
Ground
NC
No Connection Unconnected pins.
1. AMS = Most significant address
AMS = A16 for SST39LF/VF010, A17 for SST39LF/VF020, and A18 for SST39LF/VF040
T1.1 25023
©2012 Silicon Storage Technology, Inc.
5
DS25023B
06/13
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