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510FBA74M2500AAG データシートの表示(PDF) - Silicon Laboratories

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510FBA74M2500AAG
Silabs
Silicon Laboratories Silabs
510FBA74M2500AAG Datasheet PDF : 32 Pages
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Si510/511
CRYSTAL OSCILLATOR (XO) 100 kHZ TO 250 MHZ
Features
Supports any frequency from
3.3, 2.5, or 1.8 V operation
100 kHz to 250 MHz
Differential (LVPECL, LVDS,
Low jitter operation
HCSL) or CMOS output options
2 to 4 week lead times
Optional integrated 1:2 CMOS
Total stability includes 10-year
fanout buffer
aging
Runt suppression on OE and
Comprehensive production test
power on
coverage includes crystal ESR and Industry standard 5 x 7, 3.2 x 5,
DLD
and 2.5 x 3.2 mm packages
On-chip LDO regulator for power Pb-free, RoHS compliant
supply noise filtering
–40 to 85 oC operation
Applications
SONET/SDH/OTN
Gigabit Ethernet
Fibre Channel/SAS/SATA
PCI Express
Description
3G-SDI/HD-SDI/SDI
Telecom
Switches/routers
FPGA/ASIC clock generation
The Si510/511 XO utilizes Silicon Laboratories' advanced DSPLL technology
to provide any frequency from 100 kHz to 250 MHz. Unlike a traditional XO
where a different crystal is required for each output frequency, the Si510/511
uses one fixed crystal and Silicon Labs’ proprietary DSPLL synthesizer to
generate any frequency across this range. This IC-based approach allows
the crystal resonator to provide enhanced reliability, improved mechanical
robustness, and excellent stability. In addition, this solution provides superior
supply noise rejection, simplifying low jitter clock generation in noisy
environments. Crystal ESR and DLD are individually production-tested to
guarantee performance and enhance reliability. The Si510/511 is factory-
configurable for a wide variety of user specifications, including frequency,
supply voltage, output format, output enable polarity, and stability. Specific
configurations are factory-programmed at time of shipment, eliminating long
lead times and non-recurring engineering charges associated with custom
frequency oscillators.
Functional Block Diagram
VDD
OE
Low Noise Regulator
Fixed
Frequency
Oscillator
Any-Frequency
0.1 to 250 MHz
DSPLL® Synthesis
CLK+
CLK–
GND
Si5602
2.5x3.2mm
5x7mm and 3.2x5mm
Ordering Information:
See page 14.
Pin Assignments:
See page 12.
OE 1
4 VDD
GND 2
3 CLK
Si510 (CMOS)
NC 1
6 VDD
OE 2
5 CLK–
GND 3
4 CLK+
Si510(LVDS/LVPECL/HCSL/
Dual CMOS)
OOEE 11
66 VVDDDD
NNCC 22
55 CCLLKK––
GGNNDD 33
44 CCLLKK++
Si511(LVDS/LVPECL/HCSL/
Dual CMOS)
Rev. 1.4 6/18
Copyright © 2018 by Silicon Laboratories
Si510/511

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