4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9
4.10
Decoupling Guidelines ........................................................................................38
4.2.1 Voltage Rail Decoupling ...........................................................................38
Processor Clocking .............................................................................................39
4.3.1 PLL Power Supply ...................................................................................39
Voltage Identification (VID).................................................................................39
Catastrophic Thermal Protection ..........................................................................41
Reserved or Unused Signals ................................................................................41
Signal Groups ...................................................................................................41
Test Access Port (TAP) Connection .......................................................................42
Absolute Maximum and Minimum Ratings..............................................................42
DC Specifications ...............................................................................................43
4.10.1 Voltage and Current Specifications ............................................................43
4.10.2 Interface DC Specifications ......................................................................47
5 Power Management .................................................................................................54
5.1 ACPI States Supported .......................................................................................54
5.1.1 System States........................................................................................54
5.1.2 Processor Idle States...............................................................................54
5.1.3 Integrated Graphics Display States ...........................................................55
5.1.4 Integrated Memory Controller States .........................................................55
5.1.5 DMI States ............................................................................................55
5.1.6 Interface State Combinations ...................................................................55
5.2 Processor Core Power Management ......................................................................56
5.2.1 Enhanced Intel SpeedStep® Technology ....................................................56
5.2.2 Dynamic Cache Sizing .............................................................................57
5.2.3 Low-Power Idle States.............................................................................57
5.2.4 Thread C-states Description .....................................................................60
5.2.5 Processor Core/Package C-states Description..............................................61
5.3 External Thermal Sensor PM_EXTTS1#: Implementation for Fast C4/C4E Exit ............64
6 Thermal Specifications and Design Considerations...................................................66
6.1 Thermal Specifications........................................................................................66
6.1.1 Thermal Diode........................................................................................67
6.1.2 Intel® Thermal Monitor ...........................................................................69
6.1.3 Digital Thermal Sensor ............................................................................71
6.1.4 Out of Specification Detection...................................................................72
6.1.5 PROCHOT# Signal Pin .............................................................................72
7 Package Mechanical Specifications and Ball Information..........................................74
7.1 Package Mechanical Specifications .......................................................................74
7.1.1 Package Mechanical Drawings...................................................................74
7.1.2 Package Loading Specifications .................................................................75
7.2 Processor Ballout Assignment ..............................................................................75
4
Intel Confidential
Specification Update