AU80610004653AAS データシートの表示（PDF） - Intel

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AU80610004653AAS

Intel® Atom™ Processor N400 & N500 Series

Intel 

Figures

Figure 1-1

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Figure 7-10

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Figure 7-14

Platform Block Diagram ........................................................................... 14

LVDS Signals and Swing Voltage .............................................................. 34

LVDS Clock and Data Relationship ............................................................ 34

Panel Power Sequencing.......................................................................... 35

VCC and ICC Processor Loadline................................................................. 45

Idle Power Management Breakdown of the Processor Thread ........................ 58

Thread C-state ....................................................................................... 59

Processor Core Low-power States ............................................................. 59

PM_EXTTS1#/DPSLPVR Implementation for Fast C4/C4E Exit ....................... 65

Package Mechanical Drawings .................................................................. 74

Package Pinmap (Top View, Upper-Left Quadrant) ...................................... 75

Package Pinmap (Top View, Upper-Right Quadrant) .................................... 76

Package Pinmap (Top View, Lower-Left Quadrant) ...................................... 77

Package Pinmap (Top View, Lower-Right Quadrant) .................................... 78

Tables

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Table 4-30

Signal Types .......................................................................................... 15

Signal Description Buffer Types ................................................................ 15

Processor Legacy Signals......................................................................... 16

System Memory Interface........................................................................ 19

Memory Reference and Compensation ....................................................... 20

Reset and Miscellaneous Signals ............................................................... 20

DMI - Processor to Chipset Serial Interface ................................................ 21

PLL Signals ............................................................................................ 22

Analog Display Signals ............................................................................ 22

LVDS Signals ......................................................................................... 23

TAP Signals ........................................................................................... 23

Error and Thermal Protection ................................................................... 24

Processor Core Power Signals................................................................... 24

Power Signals ........................................................................................ 25

Ground ................................................................................................. 25

Supported SO-DIMM Module Configurations ............................................... 27

Supported DDR3 S0-DIMM module Configurations ...................................... 27

Analog Port Characteristics ...................................................................... 33

Panel Power Sequencing Timing Parameters............................................... 35

Voltage Identification Definition ................................................................ 39

Processor Absolute Minimum and Maximum Ratings .................................... 42

Processor Core Active and Idle Mode DC Voltage and Current Specifications ... 44

Processor I/O Buffer Supply DC Voltage and Current Specifications ............... 46

Input Clocks (BCLK, HPL_CLKIN, REFCLKIN, EXP_CLKIN) Differential

Specification .......................................................................................... 47

DDR2/DDR3 Signal Group DC Specifications............................................... 47

GTL Signal Group DC Specifications .......................................................... 48

Legacy CMOS Signal Group DC Specification .............................................. 49

Open Drain Signal Group DC Specification.................................................. 50

PWROK and RSTIN# DC Specification........................................................ 50

CPUPWRGOOD DC Specification................................................................ 50

Specification Update

5

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