Table 4-31
Table 4-32
Table 4-33
Table 4-34
Table 4-35
Table 4-36
Table 5-37
Table 5-38
Table 5-39
Table 5-40
Table 5-41
Table 5-42
Table 5-43
Table 5-44
Table 6-45
Table 6-46
Table 6-47
Table 7-48
DDR3_DRAM_PWROK DC Specification ......................................................51
TAP Signal Group DC Specification ............................................................52
CRT_DDC_DATA. CRT_DDC_CLK DC, LDDC_DATA, LDDC_CLK, LCTLA_CLK, and
LCTLB_DATA Specification .......................................................................52
CRT_HSYNC and CRT_VSYNC DC Specification............................................53
LVDS Interface DC Specification (functional operating range,
VCCLVDS = 1.8V +/- 5%) .......................................................................53
LVDD_EN, LBLKLT_EN and LBKLT_CTL DC Specification ...............................53
System States........................................................................................54
Processor Core/Package States Support .....................................................54
Integrated Graphics Display Device Control ................................................55
Main Memory States................................................................................55
DMI States ............................................................................................55
G, S and C State combinations .................................................................55
D, S and C state Combinations .................................................................56
Coordination of Thread Low-power States at the Package/Core Level .............60
Power Specifications for the Processor .......................................................67
Thermal Diode Interface ..........................................................................68
Thermal Diode Parameters using Transistor Model.......................................68
Processor Ball List by Ball Name ...............................................................79
6
Intel Confidential
Specification Update