ADG5412(Rev0) データシートの表示（PDF） - Analog Devices
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ADG5412 Datasheet PDF : 20 Pages
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ADG5412/ADG5413
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
IN1 1
16 IN2
D1 2
15 D2
S1 3 ADG5412/ 14 S2
VSS 4 ADG5413 13 VDD
GND 5 TOP VIEW 12 NC
(Not to Scale)
S4 6
11 S3
D4 7
10 D3
IN4 8
9 IN3
NC = NO CONNECT
Figure 2. TSSOP Pin Configuration
S1 1
VSS 2
GND 3
S4 4
PIN 1
INDICATOR
ADG5412/
ADG5413
TOP VIEW
(Not to Scale)
12 S2
11 VDD
10 NC
9 S3
NOTES
1. EXPOSED PAD TIED TO SUBSTRATE, VSS.
2. NC = NO CONNECT.
Figure 3. LFCSP Pin Configuration
Table 7. Pin Function Descriptions
Pin No.
TSSOP
LFCSP
Mnemonic
1
15
IN1
2
16
D1
3
1
S1
4
2
VSS
5
3
GND
6
4
S4
7
5
D4
8
6
IN4
9
7
IN3
10
8
D3
11
9
S3
12
10
NC
13
11
VDD
14
12
S2
15
13
D2
16
14
IN2
EP
Exposed Pad
Description
Logic Control Input 1.
Drain Terminal 1. This pin can be an input or output.
Source Terminal 1. This pin can be an input or output.
Most Negative Power Supply Potential.
Ground (0 V) Reference.
Source Terminal 4. This pin can be an input or output.
Drain Terminal 4. This pin can be an input or output.
Logic Control Input 4.
Logic Control Input 3.
Drain Terminal 3. This pin can be an input or output.
Source Terminal 3. This pin can be an input or output.
No Connection.
Most Positive Power Supply Potential.
Source Terminal 2. This pin can be an input or output.
Drain Terminal 2. This pin can be an input or output.
Logic Control Input 2.
The exposed pad is connected internally. For increased reliability of the solder joints
and maximum thermal capability, it is recommended that the pad be soldered to the
substrate, VSS.
Table 8. ADG5412 Truth Table
INx
1
0
Switch Condition
On
Off
Table 9. ADG5413 Truth Table
INx
0
1
S1, S4
Off
On
S2, S3
On
Off
Rev. 0 | Page 9 of 20
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