74LVC821APW,118 データシートの表示（PDF） - NXP Semiconductors.
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74LVC821APW,118
NXP Semiconductors.
74LVC821APW,118 Datasheet PDF : 20 Pages
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NXP Semiconductors
74LVC821A
10-bit D-type flip-flop; 5 V tolerance; positive-edge trigger; 3-state
5. Pinning information
5.1 Pinning
OE 1
D0 2
D1 3
D2 4
D3 5
D4 6
D5 7
D6 8
D7 9
D8 10
D9 11
GND 12
821A
24 VCC
23 Q0
22 Q1
21 Q2
20 Q3
19 Q4
18 Q5
17 Q6
16 Q7
15 Q8
14 Q9
13 CP
001aaa676
Fig 5. Pin configuration SO24 and (T)SSOP24
terminal 1
index area
D0 2
D1 3
D2 4
D3 5
D4 6
D5 7
D6 8
D7 9
D8 10
D9 11
821A
GND(1)
23 Q0
22 Q1
21 Q2
20 Q3
19 Q4
18 Q5
17 Q6
16 Q7
15 Q8
14 Q9
001aaa680
Transparent top view
(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to GND.
Fig 6. Pin configuration DHVQFN24
5.2 Pin description
Table 2.
Symbol
OE
CP
D[0:9]
Q[0:9]
GND
VCC
Pin description
Pin
1
13
2, 3, 4, 5, 6, 7, 8, 9, 10, 11
23, 22, 21, 20, 19, 18, 17, 16, 15, 14
12
24
Description
output enable input (active LOW)
clock input (LOW-to-HIGH, edge-triggered)
data input
3-state flip-flop output
ground (0 V)
supply voltage
74LVC821A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 23 November 2012
© NXP B.V. 2012. All rights reserved.
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