74LVC821AD データシートの表示（PDF） - NXP Semiconductors.
部品番号
コンポーネント説明
メーカー
74LVC821AD
NXP Semiconductors.
74LVC821AD Datasheet PDF : 20 Pages
| |||
NXP Semiconductors
74LVC821A
10-bit D-type flip-flop; 5 V tolerance; positive-edge trigger; 3-state
6. Functional description
Table 3. Function table[1]
Operating mode
Load and read register
Load register and disable outputs
Hold
Input
OE
L
L
H
H
L
CP
Dn
I
h
I
h
H or L
X
[1] H = HIGH voltage level
h = HIGH voltage level one set-up time before the LOW-to-HIGH CP transition
L = LOW voltage level
l = LOW voltage level one set-up time before the LOW-to-HIGH CP transition
Z = high-impedance OFF-state
= LOW-to-HIGH clock transition
X = don’t care
NC = no change
7. Limiting values
Internal
flip-flops
L
H
L
H
NC
Output
Qn
L
H
Z
Z
NC
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
Conditions
Min Max
Unit
VCC
supply voltage
0.5 +6.5
V
IIK
input clamping current
VI < 0 V
VI
input voltage
IOK
output clamping current
VO > VCC or VO < 0 V
VO
output voltage
HIGH or LOW state
3-state
50
[1] 0.5
-
[2] 0.5
[2] 0.5
-
mA
+6.5
V
50
mA
VCC + 0.5 V
+6.5
V
IO
output current
VO = 0 V to VCC
-
50
mA
ICC
IGND
Tstg
Ptot
supply current
ground current
storage temperature
total power dissipation
Tamb = 40 C to +125 C
-
100
mA
100 -
mA
65 +150
C
[3] -
500
mW
[1] The minimum input voltage ratings may be exceeded if the input current ratings are observed.
[2] The output voltage ratings may be exceeded if the output current ratings are observed.
[3] For SO24 package: above 70 C derate linearly with 8 mW/K.
For SSOP24 and TSSOP24 packages: above 60 C derate linearly with 5.5 mW/K.
For DHVQFN24 package: above 60 C derate linearly with 4.5 mW/K.
74LVC821A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 23 November 2012
© NXP B.V. 2012. All rights reserved.
6 of 20
Share Link: