TC7660SCPA723 データシートの表示（PDF） - Microchip Technology

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TC7660SCPA723

Super Charge Pump DC-to-DC Voltage Converter

Microchip Technology 

TC7660S

5.3 Cascading Devices

The TC7660S may be cascaded as shown (Figure 5-3)

to produce larger negative multiplication of the initial

supply voltage. However, due to the finite efficiency of

each device, the practical limit is 10 devices for light

loads. The output voltage is defined by:

EQUATION

VOUT = –nV+

where n is an integer representing the number of

devices cascaded. The resulting output resistance

would be approximately the weighted sum of the

individual TC7660S ROUT values.

5.4 Changing the TC7660S Oscillator

Frequency

It may be desirable in some applications (due to noise

or other considerations) to increase the oscillator fre-

quency. Pin 1, frequency boost pin, may be connected

to V+ to increase oscillator frequency to 45 kHz from a

nominal of 10 kHz for an input supply voltage of 5.0V.

The oscillator may also be synchronized to an external

clock as shown in Figure 5-4. In order to prevent possi-

ble device latch-up, a 1 kΩ resistor must be used in

series with the clock output. In a situation where the

designer has generated the external clock frequency

using TTL logic, the addition of a 10 kΩ pull-up resistor

to V+ supply is required. Note that the pump frequency

with external clocking, as with internal clocking, will be

half of the clock frequency. Output transitions occur on

the positive-going edge of the clock.

+

10 µF

V+

1

8

2

7

3 TC7660S 6

1 k

V+

CMOS

GATE

4 “1” 5

VOUT

10 µF

+

FIGURE 5-4:

External Clocking.

It is also possible to increase the conversion efficiency

of the TC7660S at low load levels by lowering the

oscillator frequency. This reduces the switching losses,

and is achieved by connecting an additional capacitor,

COSC, as shown in Figure 5-5. Lowering the oscillator

frequency will cause an undesirable increase in the

impedance of the pump (C1) and the reservoir (C2)

capacitors. To overcome this, increase the values of C1

and C2 by the same factor that the frequency has been

reduced. For example, the addition of a 100 pF

capacitor between pin 7 (OSC) and pin 8 (V+) will lower

the oscillator frequency to 1 kHz from its nominal

frequency of 10 kHz (a multiple of 10), and necessitate

a corresponding increase in the values of C1 and C2

(from 10 µF to 100 µF).

DS20001467C-page 10

+

C1

1

8

2

7

3 TC7660S 6

4

5

V+

COSC

VOUT

+ C2

FIGURE 5-5:

Frequency.

Lowering Oscillator

5.5 Positive Voltage Multiplication

The TC7660S may be employed to achieve positive

voltage multiplication using the circuit shown in

Figure 5-6. In this application, the pump inverter

switches of the

voltage level of

TC7660S are

V+–VF (where

used

V+ is

to charge

the supply

C1 to a

voltage

and VF is the forward voltage drop of diode D1). On the

vt(rVoa+lnt)asgifseeratchpyupcsllieec,drtehthaetrevoodulgtoahngdeCioo2dnbeCeDc1op2mlutoessctha(e2pVas+uc)ipto–prly(C2vV2o.Flt)Ta, ghoeer

twice the supply voltage minus the combined forward

voltage drops of diodes D1 and D2.

The source impedance

on the output current,

of the output

but for V+ =

(VOUT) will depend

5V and an output

current of 10 mA, it will be approximately 60Ω.

1

8

2

7

3 TC7660S 6

4

5

V+

D1

VOUT =

D2 (2 V+) - (2 VF)

+ C1 + C2

FIGURE 5-6:

Positive Voltage Multiplier.

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