CY7B923-155JC(1999) データシートの表示（PDF） - Cypress Semiconductor
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CY7B923-155JC Datasheet PDF : 35 Pages
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CY7B923
CY7B933
CY7B923/CY7B933 Electrical Characteristics Over the Operating Range[1]
Parameter
Description
Test Conditions
Min.
Max.
Unit
TTL OUTs, CY7B923: RP; CY7B933: Q0−7, SC/D, RVS, RDY, CKR, SO
VOHT
Output HIGH Voltage
IOH = − 2 mA
2.4
V
VOLT
IOST
Output LOW Voltage
Output Short Circuit Current
IOL = 4 mA
VOUT =0V[2]
0.45
V
−15
−90
mA
TTL INs, CY7B923: D0−7, SC/D, SVS, ENA, ENN, CKW, FOTO, BISTEN; CY7B933: RF, REFCLK, BISTEN
VIHT
Input HIGH Voltage
Com’l, Ind’l, & Mil
2.0
VCC
V
Ind’l & Mil (CKWandFOTO,only)
2.2
VCC
V
VILT
Input LOW Voltage
−0.5
0.8
V
IIHT
Input HIGH Current
VIN = VCC
− 10
+10
µA
IILT
Input LOW Current
VIN = 0.0V
− 500
µA
Transmitter PECL-Compatible Output Pins: OUTA+, OUTA−, OUTB+, OUTB−, OUTC+, OUTC−
VOHE
VOLE
VODIF
Output HIGH Voltage
(VCC referenced)
Output LOW Voltage
(VCC referenced)
Output Differential Voltage
|(OUT+) − (OUT−)|
Load = 50Ωto Com’l
VCC − 2V
Ind’l & Mil
Load = 50Ωto Com’l
VCC − 2V
Ind’l & Mil
Load = 50 ohms to VCC − 2V
VCC−1.03
VCC−0.83
V
VCC−1.05
VCC−0.83
V
VCC−1.86
VCC−1.62
V
VCC−1.96
VCC−1.62
V
0.6
V
Receiver PECL-Compatible Input Pins: A/B, SI, INB
VIHE
Input HIGH Voltage
Com’l
Ind’l & Mil
VILE
Input LOW Voltage
Com’l
Ind’l & Mil
IIHE[3]
IILE[3]
Input HIGH Current
Input LOW Current
VIN = VIHE Max.
VIN = VILE Min.
Differential Line Receiver Input Pins: INA+, INA−, INB+, INB−
VCC−1.165
VCC
V
VCC−1.14
VCC
V
2.0
VCC−1.475 V
2.0
VCC−1.50
V
+500
µA
+0.5
µA
VDIFF
Input Differential Voltage
|(IN+) − (IN−)|
50
mV
VIHH
Highest Input HIGH Voltage
VILL
Lowest Input LOW Voltage
IIHH
IILL[4]
Input HIGH Current
Input LOW Current
Miscellaneous
ICCT[5]
Transmitter Power Supply
Current
ICCR[6]
Receiver Power Supply
Current
VIN = VIHH Max.
VIN = VILL Min.
Freq. = Max.
Freq. = Max.
Com’l
Ind’l & Mil
Com’l
Ind’l & Mil
2.0
−200
Typ.
65
75
120
135
VCC
V
V
750
µA
µA
Max.
85
mA
95
mA
155
mA
160
mA
Notes:
1. See the last page of this specification for Group A subgroup testing information.
2. Tested one output at a time, output shorted for less than one second, less than 10% duty cycle.
3. Applies to A/B only.
4. Input currents are always positive at all voltages above VCC/2.
5. Maximum ICCT is measured with VCC = Max., one PECL output pair loaded with 50 ohms to VCC − 2.0V, and other PECL outputs tied to VCC. Typical ICCT is measured with
VCC = 5.0V, TA = 25°C, one output pair loaded with 50 ohms to VCC − 2.0V, others tied to VCC, BISTEN = LOW. ICCT includes current into VCCQ (pin 9 and pin 22) only. Current
into VCCN is determined by PECL load currents, typically 30 mA with 50 ohms to VCC − 2.0V. Each additional enabled PECL pair adds 5 mA to ICCT and an additional load
current to VCCN as described. When calculating the contribution of PECL load currents to chip power dissipation, the output load current should be multiplied by 1V instead of VCC.
6. Maximum ICCR is measured with VCC = Max., RF = LOW, and outputs unloaded. Typical ICCR is measured with VCC = 5.0V, TA = 25°C, RF = LOW, BISTEN = LOW, and
outputs unloaded. ICCR includes current into VCCQ (pins 21 and 24). Current into VCCN (pin 9) is determined by the total TTL output buffer quiescent current plus the sum of all
the load currents for each output pin. The total buffer quiescent current is 10mA max., and max. TTL load current for each output pin can be calculated as follows: Where
TITI CLPCinN+
0.95)
(VCCN *
RL
5)*0.3
)
CL *
VCCN
2
)
1.5
* Fpin
* 1.1
RL=equivalent load resistance, CL=capacitive load, and Fpin=frequency in MHz of data on pin. A derating factor of 1.1 has been included to account for worst
process corner and temperature condition.
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