CY7B923-400JI データシートの表示（PDF） - Cypress Semiconductor
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CY7B923-400JI Datasheet PDF : 33 Pages
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CY7B923
CY7B933
safety functions), the FOTO input can be asserted. While it is
possible to insure that the output state of the PECL drivers is
LOW (i.e., light is off) by sending all 0’s in Bypass mode, it is
often inconvenient to insert this level of control into the data
transmission channel, and it is impossible in Encoded mode.
FOTO is provided to simplify and augment this control function
(typically found in laser-based transmission systems). FOTO
will force OUTA+ and OUTB+ to go LOW, OUTA– and OUTB–
to go HIGH, while allowing OUTC± to continue to function
normally (OUTC is typically used as a diagnostic feedback and
cannot be disabled). This separation of function allows various
system configurations without undue load on the control
function or data channel logic.
Transmitter Serial Data Characteristics
The CY7B923 HOTLink Transmitter serial output conforms to
the requirements of the Fibre Channel specification. The serial
data output is controlled by an internal Phase-Locked Loop
that multiplies the frequency of CKW by ten (10) to maintain
the proper bit clock frequency. The jitter characteristics
(including both PLL and logic components) are shown below:
• Deterministic Jitter (Dj) < 35 ps (peak-peak). Typically
measured while sending a continuous K28.5 (C5.0).
• Random Jitter (Rj) < 175 ps (peak-peak). Typically
measured while sending a continuous K28.7 (C7.0).
Transmitter Test Mode Description
The CY7B923 Transmitter offers two types of test mode
operation, BIST mode and Test mode. In a normal system
application, the Built-In Self-Test (BIST) mode can be used to
check the functionality of the Transmitter, the Receiver, and
the link connecting them. This mode is available with minimal
impact on user system logic, and can be used as part of the
normal system diagnostics. Typical connections and timing
are shown in Figure 6.
Config
Control
and
Status
Data
Config
Control
and
Status
Data
7 MODE
4 9 22
VCC
0.01 µF
Tx PECL Load
25
82
5
24
23
8
19
18
17
FOTO
REEBINNPSNATTErCNaYns7mBOO9iUUt2teTT3rAA–+
SC/D (Da)
D0 (Db)
OUTB+
OUTB–
27
26
28
1
A
B
82
Unused Output Left
Open or Wired to VCC
0.01 µF
to Minimize Power Dissipation
16 D1 (Dc)
15
14
D2 (Dd)
D3 (De)
13
12
D4 (Di)
D5 (Df)
OUTC+
3
2
OUTC–
Tx PECL Load
270
270
11 D6 (Dg)
10 D7 (Dh)
21 SVS(Dj)
CKW
GND
130
130
A
B
0.01 µF
0.01 µF
VCC
Fiber
TX+ TX
TX–
GND
270
270
6 20
649
1500
0.01 µF
C
9 2124
26
25
MODE
REFCLK
VCC
D
Transmission
Line
Termination
RL/2
RL/2
4
23
3
BISTEN
SO CY7B933
E
5
7
A/B
RF
RDY
Receiver
28
IB+
IB–
27
E
19
18 SC/D (Qa)
17 D0 (Qb)
16 D1 (Qc)
15 D2 (Qd)
2
C
14 D3 (Qe)
IA+ 1
D
13
12
D4 (Qi)
D5 (Qf)
IA–
11
10
D6 (Qg)
D7 (Qh)
22
RVS(Qj)
CKR GND
6 8 20
Optional
Signal Det.
270
82
130
82
130
0.01 µF
Fiber Optic
PECL Load
0.01 µF
VCC
Fiber
SIG
RX+ RX
RX–
GND
Fiber Optic
Tx
Coax or
Twisted Pair
Coax or
Twisted Pair
Fiber Optic
Rx
Figure 5. HOTLink Connection Diagram
Document #: 38-02017 Rev. *E
Page 10 of 33
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