AD5251(Rev0) データシートの表示（PDF） - Analog Devices

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AD5251
(Rev.:Rev0)

Dual 64-and 256-Position I2C Nonvolatile Memory Digital Potentiometers

Analog Devices 

AD5251/AD5252

Parameter

Leakage Current

A0 Leakage Current

Input Leakage Current (Other

than WP and A0)

Input Capacitance5

POWER SUPPLIES

Single-Supply Power Range

Dual-Supply Power Range

Positive Supply Current

Negative Supply Current

Symbol

IWP

IA0

II

CI

VDD

VDD/VSS

IDD

ISS

EEMEM Data Storing Mode

Current

EEMEM Data Restoring Mode

Current6

Power Dissipation7

Power Supply Sensitivity

IDD_STORE

IDD_RESTORE

PDISS

PSS

DYNAMIC CHARACTERISTICS5, 8

Bandwidth –3 dB

Total Harmonic Distortion

VW Settling Time

Resistor Noise Voltage

Digital Crosstalk

Analog Coupling

BW

THD

tS

eN_WB

CT

CAT

Conditions

WP = VDD

A0 = GND

VIN = 0 V or VDD

Min Typ1 Max Unit

5

µA

3

µA

±1 µA

5

pF

VSS = 0 V

VIH = VDD or VIL = GND

VIH = VDD or VIL = GND, VDD = +2.5 V,

VSS = –2.5 V

VIH = VDD or VIL = GND

VIH = VDD or VIL = GND

VIH = VDD = 5 V or VIL = GND

∆VDD = 5 V ± 10%

∆VDD = 3 V ± 10%

2.7

±2.25

5

–5

5.5 V

±2.75 V

15 µA

–15 µA

35

mA

2.5

mA

−0.025 0.01

–0.04 0.02

0.075 mW

0.025 %/%

0.04 %/%

RAB = 1 kΩ

VA = 1 V rms, VB = 0 V, f = 1 kHz

VA = VDD, VB = 0 V

RWB = 500 Ω, f = 1 kHz (thermal noise only)

VA = VDD, VB = 0 V, measure VW with

adjacent RDAC making full-scale change

Signal input at A1 and measure the

output at W3, f = 1 kHz

4

MHz

0.05

%

0.2

µs

3

nV/√Hz

–80

dB

–72

dB

1 Typical represents the average reading at 25°C and VDD = 5 V.

2 Resistor position nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper

positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic, except R-DNL of AD5252 1 kΩ

version at VDD = 2.7 V, IW = VDD/R for both VDD = 3 V or VDD = 5 V.

3 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V. DNL

specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions.

4 Resistor Terminals A, B, and W have no limitations on polarity with respect to each other.

5 Guaranteed by design and not subject to production test.

6 cmd 0 NOP should be activated after cmd 1 to minimize IDD_READ current consumption.

7 PDISS is calculated from IDD × VDD = 5 V.

8 All dynamic characteristics use VDD = 5 V.

Rev. 0 | Page 4 of 28

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