AD5251(Rev0) データシートの表示（PDF） - Analog Devices
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AD5251
(Rev.:Rev0)
(Rev.:Rev0)
Analog Devices
AD5251 Datasheet PDF : 28 Pages
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I2C INTERFACE DETAIL DESCRIPTION
AD5251/AD5252
FROM MASTER TO SLAVE
FROM SLAVE TO MASTER
S = START CONDITION
P = STOP CONDITION
A = ACKNOWLEDGE (SDA LOW)
A = NOT ACKNOWLEDGE (SDA HIGH)
R/W = READ ENABLE AT HIGH AND WRITE ENABLE AT LOW
CMD/REG = COMMAND ENABLE BIT, LOGIC HIGH/REGISTER ACCESS BIT, LOGIC LOW
EE/RDAC = EEMEM REGISTER, LOGIC HIGH/RDAC REGISTER, LOGIC LOW
A4, A3, A2, A1, A0 = RDAC/EEMEM REGISTER ADDRESSES
S 0 1 0 1 1 A A 0 A CMD/ 0 EE/ A A A A A A
DD
10
REG
RDAC 4 3 2 1 0
DATA
A/ P
A
SLAVE ADDRESS
0 WRITE
0 REG
INSTRUCTIONS
AND ADDRESS
Figure 7. Single Write Mode
(1 BYTE +
ACKNOWLEDGE)
S 0 1 0 1 1 A A 0 A CMD/ 0 EE/ A A A A A A RDAC1 A RDAC3 A/ P
DD
10
REG
RDAC 4 3 2 1 0
DATA
DATA
A
RDAC SLAVE ADDRESS
0 WRITE
RDAC INSTRUCTIONS
AND ADDRESS
0 REG
Figure 8. Consecutive Write Mode
(N BYTES +
ACKNOWLEDGE)
Table 6. Addresses for Writing Data Byte Contents to RDAC Registers (R/W = 0, CMD/REG = 0, EE/RDAC = 0)
A4
A3
A2
A1
A0
RDAC
Data Byte Description
0
0
0
0
0
Reserved
0
0
0
0
1
RDAC1
6- or 8 bit wiper setting (2 MSBs of AD5251 are X)
0
0
0
1
0
Reserved
0
0
0
1
1
RDAC3
6- or 8 bit wiper setting (2 MSBs of AD5251 are X)
0
0
1
0
0
Reserved
:
:
:
:
:
0
1
1
1
1
Reserved
RDAC/EEMEM WRITE
Setting the wiper position requires an RDAC write operation.
The single write operation is shown in Figure 7, and the
consecutive write operation is shown in Figure 8. In the
consecutive write operation, if the RDAC is selected and the
address starts at 00001, the first data byte goes to RDAC1 and
the second data byte goes to RDAC3. The RDAC address is
shown in Table 6.
While the RDAC wiper setting is controlled by a specific RDAC
register, each RDAC register corresponds to a specific EEMEM
location, which provides nonvolatile wiper storage functionality.
The addresses are shown in Table 7. The single and consecutive
write operations apply also to EEMEM write operations.
There are 12 nonvolatile memory locations: EEMEM4 to
EEMEM15. Users can store a total of 12 bytes of information,
such as memory data for other components, look-up tables, or
system identification information.
In a write operation to the EEMEM registers, the device disables
the I2C interface during the internal write cycle. Acknowledge
polling is required to determine the completion of the write
cycle. See EEMEM Write-Acknowledge Polling.
Rev. 0 | Page 11 of 28
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