AD5341 データシートの表示（PDF） - Analog Devices
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AD5341 Datasheet PDF : 28 Pages
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AD5330/AD5331/AD5340/AD5341
DB8 1
DB9 2
GAIN 8
DB.. 7 20
DB0 13
CS 6
WR 7
CLR 9
LDAC 10
POWER-ON
RESET
VREF
3
VDD
12
AD5331
INPUT
REGISTER
DAC
REGISTER
10-BIT
DAC
BUFFER
4 VOUT
RESET
POWER-DOWN
LOGIC
Figure 5. AD5331 Functional Block Diagram
11
5
PD GND
DB8 1
DB9 2
VREF 3
VOUT 4
GND 5
CS 6
WR 7
GAIN 8
CLR 9
LDAC 10
10-BIT
AD5331
TOP VIEW
(Not to Scale)
20 DB7
19 DB6
18 DB5
17 DB4
16 DB3
15 DB2
14 DB1
13 DB0
12 VDD
11 PD
Figure 6. AD5331 Pin Configuration
Table 6. AD5331 Pin Function Descriptions
Pin No. Mnemonic Description
1
DB8
2
DB9
Parallel Data Input.
Most Significant Bit of Parallel Data Input.
3
VREF
Unbuffered Reference Input.
4
VOUT
Output of DAC. Buffered output with rail-to-rail operation.
5
GND
Ground reference point for all circuitry on the part.
6
CS
Active Low Chip Select Input. This is used in conjunction with WR to write data to the parallel interface.
7
WR
Active Low Write Input. This is used in conjunction with CS to write data to the parallel interface.
8
GAIN
Gain Control Pin. This controls whether the output range from the DAC is 0 V to VREF or 0 V to 2 × VREF.
9
CLR
Active low control input that clears all input registers and DAC registers to zero.
10
LDAC
Active low control input that updates the DAC registers with the contents of the input registers.
11
PD
Power-Down Pin. This active low control pin puts the DAC into power-down mode.
12
VDD
Power Supply Input. These parts can operate from 2.5 V to 5.5 V and the supply should be decoupled with a
10 μF capacitor in parallel with a 0.1 μF capacitor to GND.
13 to 20 DB0 to DB7 Eight Parallel Data Inputs.
Rev. A | Page 8 of 28
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