ADUM1400(2004) データシートの表示（PDF） - Analog Devices
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ADUM1400 Datasheet PDF : 24 Pages
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ADuM1400/ADuM1401/ADuM1402
Parameter
Symbol
Min
Typ Max Unit
Test Conditions
SWITCHING SPECIFICATIONS
ADuM140xARW
Minimum Pulse Width3
Maximum Data Rate4
Propagation Delay5
Pulse-Width Distortion, |tPLH – tPHL|5
Propagation Delay Skew6
Channel-to-Channel Matching7
PW
1
tPHL, tPLH
50
PWD
tPSK
tPSKCD/OD
1000 ns
Mbps
65 100 ns
40 ns
50 ns
50 ns
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
ADuM140xBRW
Minimum Pulse Width3
Maximum Data Rate4
Propagation Delay5
Pulse-Width Distortion, |tPLH – tPHL|5
PW
10
tPHL, tPLH
20
PWD
100 ns
Mbps
32 50 ns
3 ns
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
Change vs. Temperature
Propagation Delay Skew6
5
ps/°C CL = 15 pF, CMOS signal levels
tPSK
15 ns
CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching,
Codirectional Channels7
tPSKCD
3 ns
CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching,
Opposing-Directional Channels7
tPSKOD
6 ns
CL = 15 pF, CMOS signal levels
ADuM140xCRW
Minimum Pulse Width3
Maximum Data Rate4
Propagation Delay5
Pulse-Width Distortion, |tPLH – tPHL|5
PW
90
tPHL, tPLH
18
PWD
8.3 11.1 ns
120
Mbps
27 32 ns
0.5 2 ns
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
Change vs. Temperature
Propagation Delay Skew6
3
ps/°C CL = 15 pF, CMOS signal levels
tPSK
10 ns
CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching,
Codirectional Channels7
tPSKCD
2 ns
CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching,
Opposing-Directional Channels7
tPSKOD
5 ns
CL = 15 pF, CMOS signal levels
For All Models
Output Disable Propagation Delay
(High/Low-to-High Impedance)
tPHZ, tPLH
6 8 ns
CL = 15 pF, CMOS signal levels
Output Enable Propagation Delay
(High Impedance to High/Low)
tPZH, tPZL
6 8 ns
CL = 15 pF, CMOS signal levels
Output Rise/Fall Time (10% to 90%)
tR/tF
2.5
ns
CL = 15 pF, CMOS signal levels
Common-Mode Transient Immunity
at Logic High Output8
|CMH|
25
35
kV/µs
VIx = VDD1/VDD2, VCM = 1000 V,
transient magnitude = 800 V
Common-Mode Transient Immunity
at Logic Low Output8
|CML|
25
35
kV/µs
VIx = 0 V, VCM = 1000 V,
transient magnitude = 800 V
Refresh Rate
Input Dynamic Supply Current, per Channel9
Output Dynamic Supply Current, per Channel9
fr
IDDI (D)
IDDO (D)
1.2
Mbps
0.19
mA/Mbps
0.05
mA/Mbps
See Notes on next page.
Rev. B | Page 4 of 24
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