MU9C8248QEC データシートの表示（PDF） - Music Semiconductors

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MU9C8248QEC

FDDI SRT Interface

Music Semiconductors 

MU9C8248

INSTRUCTION SET DESCRIPTION

Instruction:

LANCAM Instruction

Binary Op Code: iiii iiii iiii iiii wce0 slll

i Instruction Code (see The LANCAM Handbook)

w The state of /W

c The state of /CM

e The state of /EC

s Stop routine

l Instruction length

This instruction transfers data or commands to or from the

LANCAM. Instructions from the LANCAM instruction set are

described in the LANCAM Handbook. The state of the control

outputs /W, /CM and /EC at the falling edge of /E for this cycle

are defined by w, c, and e. If s is set HIGH, the instruction is

the last instruction of the routine and execution of the routine is

stopped after this instruction has been executed. The length of

the instruction is determined by l. For the coding of the l bits

refer to Table 2.

Instruction:

Wait for match for yyyyB + 5 cycles, if no

match then execute at address aaaaaaB.

Binary Op Code: 0010 yyyy rraa aaaa xxx1

y Wait period

r Reserved (set LOW)

a Address

x Don't Care

after this instruction has been executed. The length of the

instruction is determined by l. For the coding of the l bits refer

to Table 2.

Instruction:

Move DA part 2 to DQ15–DQ0.

Binary Op Code: 0011 0000 0000 0010 0ce1 slll

c The state of /CM

e The state of /EC

s Stop routine

l Instruction length

This instruction places the most significant part of the DA

address (bits 47–32) on the DQ15–DQ0 lines. The control

outputs /CM and /EC at the falling edge of /E for this cycle are

defined by c and e. If s is set HIGH, the instruction is the last

instruction of the routine and execution of the routine is stopped

after this instruction has been executed. The length of the

instruction is determined by l. For the coding of the l bits refer

to Table 2.

Instruction:

Move SA part 0 to DQ15–DQ0.

Binary Op Code: 0011 0000 0000 0011 0ce1 slll

c The state of /CM

e The state of /EC

s Stop routine

l Instruction length

This instruction waits for a maximum period of yyyyB + 5 clock

cycles for the /MI input to become active. If no match condition

occurs during that period, a branch is executed to the address

which is stored in the “a” bits of the instruction. If a match

condition is detected, execution proceeds to the instruction in

the next address. This instruction is not needed for the basic

DA and/or SA comparison.

Instruction:

Move DA part 0 to DQ15–DQ0.

Binary Op Code: 0011 0000 0000 0000 0ce1 slll

c The state of /CM

e The state of /EC

s Stop routine

l Instruction length

The “Move DA part 0 to DQ15–DQ0” instruction places the

least significant part of the DA address (bits 15–0) on the

DQ15–DQ0 lines. The control outputs /CM and /EC at the

falling edge of /E for this cycle are defined by c and e. If s is set

HIGH, the instruction is the last instruction of the routine and

execution of the routine is stopped after this instruction has

been executed. The length of the instruction is determined by l.

For the coding of the l bits refer to Table 2.

Instruction:

Move DA part 1 to DQ15–DQ0.

Binary Op Code: 0011 0000 0000 0001 0ce1 slll

c The state of /CM

e The state of /EC

s Stop routine

l Instruction length

The “Move DA part 1 to DQ15–DQ0” instruction places DA

address bits 31–16 on the DQ15–DQ0 lines. The control

outputs /CM and /EC at the falling edge of /E for this cycle are

defined by c and e. If s is set HIGH, the instruction is the last

instruction of the routine and execution of the routine is stopped

The “Move SA part 0 to DQ15–DQ0” instruction places the

least significant part of the SA address (bits 15–0) on the

DQ15–DQ0 lines. The control outputs /CM and /EC at the

falling edge of /E for this cycle are defined by c and e. If s is set

HIGH, the instruction is the last instruction of the routine and

execution of the routine is stopped after this instruction has

been executed. The length of the instruction is determined by l.

For the coding of the l bits refer to Table 2.

Instruction:

Move SA part 1 to DQ15–DQ0.

Binary Op Code: 0011 0000 0000 0100 0ce1 slll

c The state of /CM

e The state of /EC

s Stop routine

l Instruction length

The “Move SA part 1 to DQ15–DQ0” instruction places SA

address bits 31–16 on the DQ15–DQ0 lines. The control

outputs /CM and /EC at the falling edge of /E for this cycle are

defined by c and e. If s is set HIGH, the instruction is the last

instruction of the routine and execution of the routine is stopped

after this instruction has been executed. The length of the

instruction is determined by l. For the coding of the l bits refer

to Table 2.

Instruction:

Move SA part 2 to DQ15–DQ0.

Binary Op Code: 0011 0000 0000 0101 0ce1 slll

c The state of /CM

e The state of /EC

s Stop routine

l Instruction length

This instruction places the most significant part of the SA

address (bits 47–32) on the DQ15–DQ0 lines. The control

outputs /CM and /EC at the falling edge of /E for this cycle are

defined by c and e. If s is set HIGH, the instruction is the last

Rev. 2.5 Web

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