MU9C8248QEC データシートの表示（PDF） - Music Semiconductors
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MU9C8248QEC Datasheet PDF : 28 Pages
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MU9C8248
PINOUT DIAGRAM
XSAMAT
81
GND
82
XDAMAT
83
CIP
84
VCC
85
/EC
86
/CM
87
/FI
88
/MI
89
GND
90
/E
91
/W
92
VCC
93
DQ15
94
DQ14
95
DQ13
96
DQ12
97
DQ11
98
DQ10
99
GND
100
MU9C8248
FDDI Interface
(Top View)
50
/HBDIR
49
A0
48
A1
47
A2
46
A3
45
A4
44
A5
43
/RESET
42
/INTEL
41
/INT
40
/FULL, /EMPTY
39
DF7
38
DF6
37
DF5
36
DF4
35
DF3
34
DF2
33
DF1
32
DF0
31
DFC
PIN DESCRIPTIONS
(/X indicates an active LOW function)
LANCAM Interface:
/CM (Data/Command Select, Output, TTL)
DQ15–DQ0 (Data Bus, Common I/O, TTL)
The DQ15–DQ0 lines transfer data, commands and status
between the MU9C8248 and the LANCAM. The direction and
nature of the information that flows between the devices are
determined by the states of /CM and /W.
/E (Chip Enable, Output, TTL)
The /E output enables the LANCAM while LOW and registers
/W, /CM, /EC and DQ15–DQ0 (if /W is LOW) on the falling
edge of /E. If /W is HIGH, data on DQ15–DQ0 from the
LANCAM is valid on the rising edge of /E.
The /CM signal determines whether DQ15–DQ0 contain
LANCAM data or commands. /CM is LOW at the falling edge
of /E for Command cycles and HIGH for Data cycles.
/EC (Enable Comparison, Output, TTL)
The /EC signal enables the LANCAM /MF pin to output the
results of a comparison. If /EC is LOW at the falling edge of /E
for a given cycle, the LANCAM /MF output is enabled on the
rising edge of /E. If /EC is HIGH, the LANCAM /MF output is
held HIGH.
/MI (Match Flag, Input, TTL)
/W (Write Enable, Output, TTL)
The /W output selects the direction of data flow during a
LANCAM cycle. DQ15–DQ0 write to the LANCAM if /W is LOW
at the falling edge of /E. Read data is output from the LANCAM
to DQ15–DQ0 on the rising edge of /E if /W is HIGH at the
falling edge of /E.
The LANCAM /MF pin takes the MU9C8248's /MI input LOW if
a valid match occurs during a Comparison cycle, and /EC was
also LOW at the start of that cycle. The state of the /MI pin
controls branching in the MU9C8248's routines and signalling
to the FDDI chipset.
Rev. 2.5 Web
2
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