MU9C8248 データシートの表示（PDF） - Music Semiconductors

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MU9C8248

FDDI SRT Interface

Music Semiconductors 

MU9C8248

/FI (Full Flag, Input, TTL)

PIN DESCRIPTIONS (CONT’D)

DCLK (Data Clock, Input, TTL)

The /FI input will be driven LOW by the LANCAM /FF output pin

if all the LANCAM memory locations have valid contents. The

status of the /FI pin can be read by the Host processor from the

MU9C8248's Control register and is also used to prevent

learning of new network addresses.

Transceiver Interface:

RCDAT7-RCDAT0 (Receive Data, Input, TTL)

The rising edge of DCLK clocks the RCDAT7-RCDAT0 data,

RCCONT, RCCONTA , RCCONTB and PARITY received from

the Physical layer device, which composed this data out of the

data received from the FDDI network.

MAC Interface:

XDAMAT (External Destination Address Match,

Output, Three-state TTL)

The RCDAT pins monitor the data received by the Physical

layer device from the FDDI network. RCDAT7-RCDAT0 are

clocked on the rising edge of DCLK. The first symbol received

from the fiber is placed on RCDAT7-RCDAT4 whereby the first

bit received from the fiber is placed on RCDAT7. For chipsets

using two associated Receive Data Control bits, each four-bit

symbol has an associated RCCONT bit to indicate whether the

four-bit symbol is to be considered a Data symbol or a Control

symbol. RCCONT B is associated with RCDAT7-RCDAT4 and

RCCONT A is associated with RCDAT3-RCDAT0. For chipsets

using one associated Receive Data Control bit, RCCONT A

becomes RCCONT and is the indicator for both symbols.

RCCONT A or RCCONT (Receive Data Control

Bit, Input, TTL)

For chipsets providing two Receive Data Control bits, RCCONT

A is associated with RCDAT3-RCDAT0 to indicate that the

four-bit symbol being presented on RCDAT3-RCDAT0 is a

Control symbol (RCCONT A is HIGH) or a Data symbol

(RCCONT A is LOW).

For chipsets using only one Control bit for each symbol pair,

RCCONT A becomes RCCONT and is the only Receive Data

Control bit used. If RCCONT is HIGH, both RCDAT7-RCDAT4

and RCDAT3-RCDAT0 are Control symbols. If RCCONT is

LOW, both RCDAT7-RCDAT4 and RCDAT3-RCDAT0 are Data

symbols. RCCONT A or RCCONT is valid on the rising edge of

DCLK.

RCCONT B (Receive Data Control Bit, Input, TTL)

RCCONT B is provided by the Physical layer devices, is valid

on the rising edge of DCLK, and is used to indicate that the

four-bit symbol being presented on RCDAT7-RCDAT4 is a

Control symbol (RCCONT B is HIGH) or a Data symbol

(RCCONT B is LOW). For FDDI chipsets which use only one

control bit RCCONT B should be tied to GND.

PARITY (Parity, Input, TTL)

This input signal is the ODD parity of the RCDAT bus and

RCCONT when the MU9C8248 is used in National

Semiconductors (NS) mode. It is the ODD parity of the RCDAT

bus and RCCONT A and -B when the MU9C8248 is

programmed in not NS mode.

XDAMAT indicates, when made active, the FDDI chipset to

copy a FDDI frame (this decision is made on basis of the

Destination Address of the frame currently being received). The

duration and polarity of XDAMAT are set in the Transparent

Bridging/MAC register.

XSAMAT (External Source Address Match,

Output, Three-state TTL)

XSAMAT, when active, indicates that the Source Address of

the frame currently being received is found in the LANCAM

database. The duration and polarity of XSAMAT are set in the

Transparent Bridging/MAC register.

SRMAT (Source Routing Match, Output,

Three-state TTL)

SRMAT, when active, indicates that the frame currently being

received should be copied and forwarded based on information

in the Routing Information Field of that frame. The duration and

polarity of SRMAT are set in the Transparent Bridging/MAC

register.

ABORT (Abort, Output, Three-state TTL)

ABORT is used to notify the FDDI chipset that the frame

currently being received should not be copied and forwarded.

The duration and polarity of ABORT are set in the Transparent

Bridging/MAC register.

CIP (Compare in Progress, Output, TTL)

CIP is an output signal that National Semiconductors needs to

notify their system interface that a Compare is in Progress.

CIP goes HIGH on the third rising edge of DCLK after the edge

that loaded a valid FC field into the MU9C8248. CIP returns

LOW on the seventh rising edge of DCLK after the last byte of

the Source Address field for frames not containing a Routing

Information Field (RIF), or on the seventh rising edge of DCLK

after the last byte of the RIF, if the frame contains such a field.

Rev. 2.5 Web

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