AD7883BN データシートの表示（PDF） - Analog Devices
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AD7883BN Datasheet PDF : 12 Pages
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AD7883
TIMING CHARACTERISTICS1 (VSS = +3 V to +3.6 V, VREF = VDD, AGND = DGND = 0 V)
Parameter
Limit at +25؇C
(All Versions)
Limit at TMIN, TMAX
(All Versions)
Units
Conditions/Comments
t1
50
60
t2
200
200
t3
0
0
t4
0
0
t5
0
0
t6
110
150
t72
100
140
t83
5
5
90
90
ns min
ns max
ns min
ns min
ns min
ns min
ns max
ns min
ns max
CONVST Pulse Width
CONVST to BUSY Falling Edge
BUSY to CS Setup Time
CS to RD Setup Time
CS to RD Hold Time
RD Pulse Width
Data Access Time after RD
Bus Relinquish Time after RD
NOTES
1Timing specifications in bold print are 100% production tested. All other times are sample tested at +25 °C to ensure compliance. All input signals are specified with
tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
2t7 is measured with the load circuit of Figure 2 and defined as the time required for an output to cross 0.8 V or 2.4 V.
3t8 is derived from the measured time taken by the data outputs to change by 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapo-
lated back to remove the effects of charging the 50 pF capacitor. This means that the time, t 8, quoted in the timing characteristics is the true bus relinquish time of
the part and as such is independent of external bus loading capacitances.
CONVST
BUSY
CS
RD
DB0 – DB11
t1
t2
TRACK/HOLD
GOES INTO HOLD
tCONVERT
t3
t4
t5
t6
THREE-STATE
t7
t8
DATA
VALID
Figure 1. Timing Diagram
0.8mA
TO
OUTPUT
PIN
50pF
200µA
+1.6V
Figure 2. Load Circuit for Access and Relinquish Time
Table I. Truth Table
CS
CONVT
RD
Function
1
1
1
j
0
1
0
1
X
Not Selected
1
Start Conversion g
0
Enable ADC Data
1
Data Bus Three Stated
ORDERING GUIDE
Model
AD7883BN
AD7883BR
Temperature Range
–40°C to +85°C
–40°C to +85°C
Package Option*
N-24
R-24
*N = Plastic DIP; R = SOIC (Small Outline Integrated Circuit).
REV. 0
–3–
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