AS1340 データシートの表示（PDF） - Unspecified

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AS1340

50V, Micropower, DC-DC Boost Converter

Unspecified 

AS1340

Datasheet - Detailed Description

8 Detailed Description

The AS1340 features a current limiting circuitry, a fixed-frequency PWM architecture, power-OK circuitry, thermal protection, and an automatic

powersave mode in a tiny package, and maintains high efficiency at light loads.

Figure 27. AS1340 - Block Diagram with Shutdown Disconnect Switch

VIN = 2.7V

to 5.5V

CIN

1µF

2

VCC

1

EN

3 SWVIN 6 SWOUT

L1

4.7µH

4 POK

PWM

Control

1 MHz

Spread

Spectrum

Ramp Gen-

erator

+

PWM

Comp

–

–

Slope

Compensator

Shutdown

Control

Shutdown

RC

Powersave

CC

Powersave

Operation

Control

Sync Drive

Control



CP2

5 LX

–

VOUT

Good

+

1.13V

0.9

Current

Sense

AS1340

–

VC gm Error

Amp +

CFF*

8

FB

1.25V

Ref

7,9 GND

VIN to 50V

R1

COUT

R2

* Optional

Automatic powersave mode regulates the output and also reduces average current flow into the device, resulting in high efficiency at light loads.

When the output increases sufficiently, the powersave comparator output remains high, resulting in continuous operation.

For each oscillator cycle, the power switch is enabled. A voltage proportional to switch current is added to a stabilizing ramp and the resulting

sum is delivered to the positive terminal of the PWM comparator.

The error amplifier compares the voltage at FB with the internal 1.25V reference and generates an error signal (VC). When VC is below the

powersave mode threshold voltage the automatic powersave-mode is activated and the hysteretic comparator disables the power circuitry, with

only the low-power circuitry still active (total current consumption is minimized).

When a load is applied, VFB decreases; VC increases and enables the power circuitry and the device starts switching. In light loads, the output

voltage (and the voltage at FB) will increase until the powersave comparator disables the power circuitry, causing the output voltage to decrease

again. This cycle is repeated resulting in low-frequency ripple at the output.

The POK output indicates whether the output voltage is within 90% of the nominal output voltage level or not. When EN is low, the circuit is not

active and POK gives a high signal when connected to VCC by a pull-up resistor. When EN goes high, POK goes low after approximately 50µs

and will go high when the output reaches 90% of the nominal output voltage (see Figure 20 on page 7). When input and output voltage are

almost the same, it may happen that the POK Signal does not go low because VOUT reaches 90% before the delay has expired. The open-drain

POK output sinks current, when EN is high and the output voltage is below 90% of the nominal output voltage.

Thermal protection circuitry shuts down the device when its temperature reaches 145ºC.

www.ams.com/DC-DC_Step-Up/AS1340

Revision 1.20

9 - 17

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