MCIMX280DVM4B データシートの表示（PDF） - Freescale Semiconductor

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MCIMX280DVM4B

i.MX28 Applications Processors Data Sheet for Consumer Products

Freescale Semiconductor 

Table 4. i.MX28 Digital and Analog Modules (continued)

Block

Mnemonic

BCH

BSI

CLKCTRL

DCP

DFLPT

DIGCTL

DUART

EMI

ENET

FlexCAN(2)

GPMI

Block Name Subsystem

Brief Description

Bit-correcting Connectivity

ECC

peripherals

accelerator

The Bose, Ray-Chaudhuri, Hocquenghem (BCH) Encoder and Decoder

module is capable of correcting from 2 to 20 single bit errors within a block of

data no larger than about 900 bytes (512 bytes is typical) in applications such

as protecting data and resources stored on modern NAND flash devices.

Boundary Connectivity

Scan Interface peripherals

The boundary scan interface is provided to enable board level testing.

There are five pins on the device which is used to implement the IEEE Std

1149.1™ boundary scan protocol.

Clock control Clocks

module

The clock control module, or CLKCTRL, generates the clock domains for all

components in the i.MX28 system. The crystal clock or PLL clock are the two

fundamental sources used to produce most of the clock domains. For lower

performance and reduced power consumption, the crystal clock is selected.

The PLL is selected for higher performance requirements but requires

increased power consumption. In most cases, when the PLL is used as the

source, a Phase Fractional Divider (PFD) can be programmed to reduce the

PLL clock frequency by up to a factor of 2.

Data

Security

co-processor

This module provides support for general encryption and hashing functions

typically used for security functions. Because its basic job is moving data

from memory to memory, it also incorporates a memory-copy (memcopy)

function for both debugging and as a more efficient method of copying data

between memory blocks than the DMA-based approach.

Default

System control The DFLPT provides a unique method of implementing the ARM MMU

first-level page

first-level page table (L1PT) using a hardware-based approach.

table

Digital control System control The digital control module includes sections for controlling the SRAM, the

and on-chip

performance monitors, high-entropy pseudo-random number seed,

RAM

free-running microseconds counter, and other chip control functions.

Debug UART Connectivity

peripherals

The Debug UART performs the following data conversions:

• Serial-to-parallel conversion on data received from a peripheral device

• Parallel-to-serial conversion on data transmitted to the peripheral device

External

memory

interface

Connectivity

peripherals

The i.MX28 supports off-chip DRAM storage through the EMI controller,

which is connected to the four internal AHB/AXI busses. The EMI supports

multiple external memory types, including:

• 1.8-V Mobile DDR1 (LP-DDR1)

• Standard 1.8-V DDR2

• Low Voltage 1.5-V DDR2 (LV-DDR2)

Ethernet MAC Connectivity

Controller peripherals

Ethernet MAC controller connected to the uDMA (unified DMA). Supports

10/100 Mbps with TCP/UDP/IP Acceleration and IEEE 1588 Functions; also

supports RMII or MII connectivity.

Controller Connectivity

area network peripherals

module

The Controller Area Network (CAN) protocol is a message based protocol

used for serial data. It was designed specifically for automotive but is also

used in industrial control and medical applications. The serial data bus runs

at 1 Mbps.

General-pur- Connectivity

pose media peripherals

interface

The General-Purpose Media Interface (GPMI) controller is a flexible NAND

flash controller with 8-bit data width, up to 50-MBps I/O speed and individual

chip select and DMA channels for up to 8 NAND devices. It also provides a

interface to 20-bit BCH for ECC.

i.MX28 Applications Processors Data Sheet for Consumer Products, Rev. 1

Freescale Semiconductor

7

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