SST49LF008A データシートの表示（PDF） - Microchip Technology

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SST49LF008A

8 Mbit Firmware Hub

Microchip Technology 

A Microchip Technology Company

8 Mbit Firmware Hub

SST49LF008A

Product Description

Data Sheet

The SST49LF008A flash memory devices are designed to be read-compatible with the Intel® 82802

Firmware Hub (FWH) device for PC-BIOS application. These devices provide protection for the storage

and update of code and data in addition to adding system design flexibility through five general pur-

pose inputs. Two interface modes are supported by the SST49LF008A: Firmware Hub (FWH) Interface

mode for in-system programming and Parallel Programming (PP) mode for fast factory programming of

PC-BIOS applications.

The SST49LF008A flash memory devices are manufactured with SST’s proprietary, high performance

SuperFlash technology. The split-gate cell design and thick-oxide tunneling injector attain better reli-

ability and manufacturability compared with alternate approaches. The SST49LF008A devices signifi-

cantly improve performance and reliability, while lowering power consumption.

The SST49LF008A devices write (Program or Erase) with a single 3.0-3.6V power supply. They use

less energy during Erase and Program than alternative flash memory technologies. The total energy

consumed is a function of the applied voltage, current and time of application. Since for any given volt-

age range, the SuperFlash technology uses less current to program and has a shorter Erase time, the

total energy consumed during any Erase or Program operation is less than alternative flash memory

technologies. The SST49LF008A products provide a maximum Byte-Program time of 20 µsec. The

entire memory can be erased and programmed byte-by-byte typically in 15 seconds when using status

detection features such as Toggle Bit or Data# Polling to indicate the completion of Program operation.

The SuperFlash technology provides fixed Erase and Program times independent of the number of

Erase/Program cycles performed. Therefore the system software or hardware does not have to be cal-

ibrated or correlated to the cumulated number of Erase/Program cycles as is necessary with alterna-

tive flash memory technologies, whose Erase and Program time increase with accumulated Erase/

Program cycles.

To protect against inadvertent write, the SST49LF008A devices employ hardware and software data

(SDP) protection schemes. It is offered with typical endurance of 100,000 cycles. Data retention is

rated at greater than 100 years.

To meet high density, surface mount requirements, the SST49LF008A devices are offered in a 32-lead

TSOP package. In addition, the SST49LF008A is offered in 32-lead PLCC and 40-lead TSOP pack-

ages. See Figures 2, 3, and 4 for pin assignments and Table 1 for pin descriptions.

©2011 Silicon Storage Technology, Inc.

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