SST49LF008A データシートの表示（PDF） - Microchip Technology

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SST49LF008A

8 Mbit Firmware Hub

Microchip Technology 

A Microchip Technology Company

8 Mbit Firmware Hub

SST49LF008A

Firmware Hub (FWH) Mode

Data Sheet

Device Operation

The FWH mode uses a 5-signal communication interface, FWH[3:0] and FWH4, to control operations

of the SST49LF008A. Operations such as Memory Read and Memory Write uses Intel FWH propriety

protocol. JEDEC Standard SDP (Software Data Protection) Byte-Program, Sector-Erase and Block-

Erase command sequences are incorporated into the FWH memory cycles. Chip-Erase is only avail-

able in PP Mode.

The device enters standby mode when FWH4 is high and no internal operation is in progress. The

device is in ready mode when FWH4 is low and no activity is on the FWH bus.

Firmware Hub Interface Cycles

Addresses and data are transferred to and from the SST49LF008A by a series of “fields,” where each

field contains 4 bits of data. SST49LF008A supports only single-byte Read and Write, and all fields are

one clock cycle in length. Field sequences and contents are strictly defined for Read and Write opera-

tions. Addresses in this section refer to addresses as seen from the SST49LF008A’s “point of view,”

some calculation will be required to translate these to the actual locations in the memory map (and

vice versa) if multiple memory devices are used on the bus. Tables 3 and 4 list the field sequences for

Read and Write cycles.

©2011 Silicon Storage Technology, Inc.

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