MD1211
AC Electrical Characteristics
Symbol Parameter
tPLH
tPHL
tr
tf
l tr - tf l
l tPLH-tPHL l
∆tdm
Propagation delay when output is from
low to high
Propagation delay when output is from
high to low
Output rise time
Output fall time
Rise and fall time matching
Propagation low to high and high to low
matching
Propagation delay match
Min Typ Max Units Conditions
-
10
-
ns
CLOAD = 1000pF, (see timing
-
10
-
ns diagram)
-
10
-
ns Input signal rise/fall time 2ns
-
10
-
ns
-
2.0
-
ns
For each channel
-
2.0
-
ns
-
3.0
-
ns Device to device delay match
Timing Diagram
3.3V
IN
0V
50%
tPLH
50%
tPHL
OUT
0V
90%
10%
tr
90%
10%
tf
Pin Description
Pin #
Function
1
VLL
2
INA
3
GND
4
INB
5
OUTB
6
VDD
7
OUTA
8
VDD
Description
Logic supply voltage
Logic input
Device ground
Logic input
Output driver
Main supply voltage
Output driver
Main supply voltage
VLL 1
INA 2
MD1211
8 VDD
7 OUTA
GND 3
6 VDD
INB 4
5 OUTB
NR011806
3