AT88SA10HS(2009) データシートの表示（PDF） - Atmel Corporation

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AT88SA10HS
(Rev.:2009)

CryptoAuthentication Host Security Chip

Atmel Corporation 

1.6.

Security Features

The AT88SA10HS incorporates a number of physical security features designed to protect the keys from release.

These include an active shield over the entire surface of the part, internal memory encryption, internal clock generation,

glitch protection, voltage tamper detection and other physical design features.

Pre-programmed keys stored on the AT88SA10HS are encrypted in such a way as to make retrieval of their values via

outside analysis very difficult.

Both the clock and logic supply voltage are internally generated, preventing any direct attack via the pins on these two

signals.

2. IO Protocol

Communications to and from the AT88SA10HS take place over a single asynchronously timed wire using a pulse count

scheme. The overall communications structure is a hierarchy:

Table 2.

Tokens

Flags

Blocks

Packets

IO Hierarchy

Implement a single data bit transmitted on the bus, or the wake-up event.

Comprised of eight tokens (bits) which convey the direction and meaning of the next group of bits (if any)

which may be transmitted.

Data following the command and transmit flags. They incorporate both a byte count and a checksum to

ensure proper data transmission.

Bytes forming the core of the block without the count and CRC. They are either the input or output

parameters of the AT88SA10HS command or status information from the AT88SA10HS.

Refer to Applications Notes on Atmel’s website for more details on how to use any microprocessor to easily generate

the signaling necessary to send these values to the chip.

2.1.

IO Tokens

There are a number of IO tokens that may be transmitted along the bus:

Input: (To AT88SA10HS)

Wake Wake the AT88SA10HS up from sleep (low power) state

Zero

Send a single bit from system to the AT88SA10HS with a value of 0

One

Send a single bit from system to the AT88SA10HS with a value of 1

Output: (From AT88SA10HS)

ZeroOut Send a single bit from the AT88SA10HS to the system with a value of 0

OneOut Send a single bit from the AT88SA10HS to the system with a value of 1

The waveforms are the same in either direction, however there are some differences in timing based on the

expectation that the host has a very accurate and consistent clock while the AT88SA10HS has significant variation in

its internal clock generator due to normal manufacturing and environmental fluctuations.

The bit timings are designed to permit a standard UART running at 230.4K baud to transmit and receive the tokens

efficiently. Each byte transmitted or received by the UART corresponds to a single bit received or transmitted by the

AT88SA10HS. Refer to Applications Notes on Atmel’s website for more details.

4 AT88SA10HS Host Authentication Chip [Preliminary]

8595B–SMEM–09/09

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