FSL4110LR データシートの表示（PDF） - Fairchild Semiconductor
部品番号
コンポーネント説明
メーカー
FSL4110LR Datasheet PDF : 15 Pages
| |||
Power
VDS
on
Fault
occurs
Fault
removed
t
VCC
VAUX
VSTART
VHVREG
VSTOP
Normal Fault condition
operation Restart time (1.6 s)
t
Normal
operation
Figure 19. Auto-Restart Protection Waveforms
3.1. Overload Protection (OLP)
Overload is defined as the load current exceeding its
normal level due to an unexpected abnormal event. In
this situation, the protection circuit should trigger to
protect the SMPS. However, even when the SMPS is in
normal operation, the overload protection circuit can be
triggered during load transition. To avoid this undesired
operation, the overload protection circuit is designed to
trigger only after a specified time to determine whether
it is a transient situation or a true overload situation.
Because of the pulse-by-pulse current-limit capability,
the maximum peak current through the SenseFET is
limited. If the output consumes more than this maximum
power, the output voltage decreases below the set
voltage. This reduces the current through the opto-
diode, which also reduces the opto-coupler transistor
current, thus increasing the feedback voltage (VFB). If
VFB exceeds 2.4 V, internal diode D1 is blocked and the
current (IDLY) by RDLY starts to charge CFB. If feedback
voltage reaches 4.4 V, internal fixed delay time (tDELAY)
starts counting. If feedback voltage maintains over
4.4 V after tDELAY (100 ms), the switching operation is
terminated (see Figure 20). The internal OLP circuit is
shown in Figure 21.
VCC
VAUX
VSTART
VHVREG
VSTOP
tDELAY
t
VFB
tDLY
4.4 V
2.4 V
tRESTART
t
IDS
t
Overload
Occurrence
Overload
Disappear
Figure 20. OLP Waveforms
VCC
IDLY
RDLY
3
FB
CFB
VREF
IFB
3R
D1 D2
R
Line
Comp.
OSC
PWM
SQ
RQ
LEB
OLP
VOLP
100 ms
Delay
OLP
Drain
6,7
Gate
Driver
RSENSE
1 GND
Figure 21. OLP Circuit
Recommended the RDLY value is less than 5 MΩ in self-
biasing. The delay time (tDLY) can be calculated by
equation (3).
t DLY
RDLY
CFB
ln1 VCC
2
2.4
(3)
Example:
When, RDLY = 3 MΩ, CFB = 68 nF, VCC = 15 V,
tDLY = 35 ms
∴ Total delay time for OLP: 135 ms
3.2. Abnormal Over-Current Protection (AOCP)
When the secondary rectifier diodes or the transformer
pins are shorted, a steep current with extremely high
di/dt can flow through the SenseFET during the
minimum turn-on time. Overload protection is not
enough to protect the FSL4110LR in that abnormal
case (see Figure 22); since severe current stress is
imposed on the SenseFET until OLP is triggered. The
internal AOCP circuit is shown in Figure 23. When the
gate turn-on signal is applied to the power SenseFET,
the AOCP block is enabled and monitors the current
through the sensing-resistor. The voltage across the
resistor is compared with a preset AOCP level. If the
sensing resistor voltage is greater than the AOCP level,
the high signal is applied to input of the NOR gate,
resulting in the shutdown of the SMPS.
VCC
VAUX
VSTART
VHVREG
VSTOP
tRESTART
t
IDS
t
AOCP
Occurrence
AOCP
Disappear
Figure 22. AOCP Waveforms
© 2014 Fairchild Semiconductor Corporation
FSL4110LR • Rev. 1.3
10
www.fairchildsemi.com
Share Link: 