IRLR/U120NPbF
Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
Parameter
Min. Typ. Max. Units
Conditions
V(BR)DSS Drain-to-Source Breakdown Voltage
100 ––– ––– V VGS = 0V, ID = 250μA
ΔV(BR)DSS/ΔTJ Breakdown Voltage Temp. Coefficient ––– 0.12 ––– V/°C Reference to 25°C, ID = 1mA
RDS(on)
Static Drain-to-Source On-Resistance
––– ––– 0.185
VGS = 10V, ID = 6.0A
––– ––– 0.225 Ω VGS = 5.0V, ID = 6.0A
––– ––– 0.265
VGS = 4.0V, ID = 5.0A
VGS(th)
Gate Threshold Voltage
1.0 ––– 2.0 V VDS = VGS, ID = 250μA
gfs
Forward Transconductance
3.1 ––– ––– S VDS = 25V, ID = 6.0A
IDSS
Drain-to-Source Leakage Current
––– ––– 25
––– ––– 250
μA VDS = 100V, VGS = 0V
VDS = 80V, VGS = 0V, TJ = 150°C
IGSS
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
––– ––– 100 nA VGS = 16V
––– ––– -100
VGS = -16V
Qg
Total Gate Charge
––– ––– 20
ID = 6.0A
Qgs
Qgd
td(on)
tr
td(off)
tf
LD
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Internal Drain Inductance
––– ––– 4.6 nC VDS = 80V
––– ––– 10
VGS = 5.0V, See Fig. 6 and 13
––– 4.0 –––
VDD = 50V
––– 35 ––– ns ID = 6.0A
––– 23 –––
RG = 11Ω, VGS = 5.0V
––– 22 –––
RD = 8.2Ω, See Fig. 10
Between lead,
D
4.5 nH 6mm (0.25in.)
LS
Internal Source Inductance
––– 7.5 –––
from package
G
and center of die contact
S
Ciss
Input Capacitance
Coss
Output Capacitance
Crss
Reverse Transfer Capacitance
––– 440 –––
––– 97 –––
––– 50 –––
VGS = 0V
pF VDS = 25V
ƒ = 1.0MHz, See Fig. 5
Source-Drain Ratings and Characteristics
Parameter
IS
Continuous Source Current
(Body Diode)
ISM
Pulsed Source Current
(Body Diode)
VSD
Diode Forward Voltage
trr
Reverse Recovery Time
Qrr
Reverse RecoveryCharge
ton
Forward Turn-On Time
Min. Typ. Max. Units
Conditions
––– ––– 10
––– ––– 35
––– ––– 1.3
––– 110 160
––– 410 620
MOSFET symbol
D
A showing the
integral reverse
G
p-n junction diode.
S
V TJ = 25°C, IS = 6.0A, VGS = 0V
ns TJ = 25°C, IF =6.0A
nC di/dt = 100A/μs
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Notes:
Repetitive rating; pulse width limited by
max. junction temperature. ( See fig. 11 )
Pulse width ≤ 300μs; duty cycle ≤ 2%.
VDD = 25V, starting TJ = 25°C, L = 4.7mH
This is applied for I-PAK, LS of D-PAK is measured between lead and
RG = 25Ω, IAS = 6.0A. (See Figure 12)
center of die contact
ISD ≤ 6.0A, di/dt ≤ 340A/μs, VDD ≤ V(BR)DSS, Uses IRL520N data and test conditions.
TJ ≤ 175°C
** When mounted on 1" square PCB (FR-4 or G-10 Material ) .
For recommended footprint and soldering techniques refer to application note #AN-994
2
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July 9, 2014