MAX14515 データシートの表示（PDF） - Maxim Integrated

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MAX14515

High-Voltage Liquid Lens Driver

Maxim Integrated 

High-Voltage Liquid Lens Driver

Detailed Description

The MAX14515 high-voltage liquid lens driver utilizes a

charge-pump-based boost converter and integrated H-

bridge to provide a compact lens driver solution with min-

imal external components. This device features an 8-bit

monotonic DAC controlled by a simple 2-wire I2C inter-

face to set the peak amplitude of the high-voltage output.

Power-On Reset

When the MAX14515 initially powers up, all the regis-

ters are cleared and the device is in sleep mode.

High-Voltage Outputs (VA, VB)

Connect a liquid lens in between the high-voltage out-

puts (VA, VB) of the MAX14515. The peak output voltage

of VA and VB is controlled by the value set in the high-

voltage output register (VP). (See Register Definition).

The internal H-bridge that drives VA and VB switches at

1.1kHz (typ).

Reference Output (VREF)

VREF is the internal 5V charge-pump reference voltage

of the MAX14515. Connect a 1µF ceramic capacitor

from VREF to GND. VREF is not intended to drive exter-

nal circuitry.

Shutdown Mode (EN)

The MAX14515 features a shutdown mode that reduces

supply current to less than 500nA (max). In shutdown,

all registers are in a reset state, and the I2C interface is

disabled. Drive EN low to place the device in shutdown

mode. Drive EN high for normal operation. Driving EN

rail-to-rail minimizes power consumption.

Sleep Mode

When EN is high and the sleep mode bit (SM) in the

power mode register (see Register Definition) is reset,

the device is in sleep mode. During sleep mode, only

the power-on reset circuit remains active. If no activity

is detected on the I2C interface, current consumption is

less than 3µA.

I2C Serial Interface

Serial Addressing

The MAX14515 operates as a slave device that sends

and receives data through an I2C-compatible 2-wire

interface. The interface uses a serial-data line (SDA)

and a serial-clock line (SCL) to achieve bidirectional

communication between master(s) and slave(s). A

master (typically a microcontroller) initiates all data

transfers to and from the MAX14515, and generates the

SCL clock that synchronizes the data transfer. The SDA

line operates as both an input and an open-drain out-

put. A pullup resistor is required on SDA. The SCL line

Register Definition

DEVICE ADDRESS

FIELD NAME READ WRITE

BITS

POWER MODE (I2C ADDRESS = 0x00)

RSVD

Read/Write

[7:1]

POWER-ON

RESET

0000 000

SM

Read/Write

0

0

HIGH-VOLTAGE OUTPUT LEVEL (I2C ADDRESS = 0x01)

WRITE

READ

DESCRIPTION

0xEC

0xED

Reserved. All bits must be set to 0.

Sleep Mode Bit

0 = Sleep Mode

1 = Normal Operation

All the registers keep the same values as before sleep unless

a POR occurs.

Code 0x00 = 0VPEAK

Code 0x01 = 10VPEAK

VP(7:0)

Read/Write

[7:0]

0000 0000 Code 0xFF = 49.5VPEAK, linear scale.

VOUT(PEAK) = 9.5VPEAK + 0.1575VPEAK x (N - 1)

where N = Code 0x01 to 0xFF in decimal. Accuracy (±3%).

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