KSZ8041FTL データシートの表示（PDF） - Micrel

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KSZ8041FTL

10Base-T/100Base-TX/100Base-FX Physical Layer Transceiver

Micrel 

Micrel, Inc.

KSZ8041TL/FTL

List of Figures

Figure 1. Auto-Negotiation Flow Chart................................................................................................................................. 19

Figure 2. SMII Transmit Data/Control Segment................................................................................................................... 25

Figure 3. SMII Receive Data/Control Segment.................................................................................................................... 26

Figure 4. Typical Straight Cable Connection ....................................................................................................................... 27

Figure 5. Typical Crossover Cable Connection ................................................................................................................... 28

Figure 6. 25MHz Crystal / Oscillator Reference Clock for MII Mode ................................................................................... 30

Figure 7. 50MHz Oscillator Reference Clock for RMII Mode............................................................................................... 30

Figure 8. 125MHz Oscillator Reference Clock for SMII Mode ............................................................................................. 30

Figure 9. KSZ8041TL/FTL Power and Ground Connections............................................................................................... 31

Figure 10. KSZ8041FTL / KSZ8041TL Back-to-Back Media Converter .............................................................................. 33

Figure 11. MII SQE Timing (10Base-T) ............................................................................................................................... 45

Figure 12. MII Transmit Timing (10Base-T) ......................................................................................................................... 46

Figure 13. MII Receive Timing (10Base-T) .......................................................................................................................... 47

Figure 14. MII Transmit Timing (100Base-TX)..................................................................................................................... 48

Figure 15. MII Receive Timing (100Base-TX)...................................................................................................................... 49

Figure 16. RMII Timing – Data Received from RMII ............................................................................................................ 50

Figure 17. RMII Timing – Data Input to RMII ....................................................................................................................... 50

Figure 18. Auto-Negotiation Fast Link Pulse (FLP) Timing ................................................................................................. 51

Figure 19. MDC/MDIO Timing.............................................................................................................................................. 52

Figure 20. Reset Timing....................................................................................................................................................... 53

Figure 21. Recommended Reset Circuit.............................................................................................................................. 54

Figure 22. Recommended Reset Circuit for Interfacing with CPU/FPGA Reset Output ..................................................... 54

Figure 23. Reference Circuits for LED Strapping Pins......................................................................................................... 55

April 2007

6

M9999-042707-1.1

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