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MAX769 データシートの表示(PDF) - Maxim Integrated

部品番号
コンポーネント説明
メーカー
MAX769
MaximIC
Maxim Integrated MaximIC
MAX769 Datasheet PDF : 16 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
2 or 3-Cell, Step-Up/Down,
Two-Way Pager System IC
2 OR 3-CELL
AA ALKALINE
BATTERY
R1
1M
REG1 R2
250k
R5
270k
A/D IN
SERIAL
I/O
1.8
DRIVERS
11 LBI
6 LBO
9 CH0
27 CS
5 SCL
2 SDI
3 SDO
17 DR1
19 DR2
18 DR2IN
16 DRGND
38.4kHz
C10
22nF
10k
13
12
C9
1nF
SYNC
FILT
8 REF
C8
1µF
26
BATT
MAX769
AGND
15
C5
22µF
1
LX1
LX2 28
OUT 25
PGND 4
24
REG1
R2IN 22
OFS 14
COFS
0.1µF
21
REG2
20
REG3
RSIN 10
RSO 7
23
NICD
L1
68µH
D1
MBR0520L
C2
10µF
ROFS, 15k
C1
47µF
3.0V
LOGIC
C3
10µF
C4
1µF 100k
2.85V
ANALOG
1V RCVR
R3
1.3M
R4
470k
TO RF
PA TO µC
RESET
3-CELL
NiCd
C6
0.1µF
Figure 2. Standard Application Circuit
7-Bit ADC (CH0 Input and CH1, CH2)
Three analog channels are compared to a 7-bit, serially
programmed digital-to-analog converter (CH DAC). The
CH DAC voltage can be varied in 10mV steps from
200mV to VREF - 1LSB (or 1.27V) (Table 1). CH0 is an
external input, while CH1 and CH2 are signals internally
generated from the NICD and BATT pins. NICD and
BATT are internally divided by four before being com-
pared to CH DAC. The comparison threshold voltages
for each channel are described in the following equa-
tions:
VTH (CH0: pin 9) = D x 10mV
VTH (CH1: NICD) = D x 40mV
VTH (CH2: BATT) = D x 40mV
where D is the decimal equivalent of the binary code
DAC0–DAC6 (Table 1). DAC0 is the LSB. A DAC code
of 1111111 equates to D = 127. When all zeros are pro-
grammed, the CH DAC and CH_ comparators turn off.
CH0, CH1, and CH2 comparison results reside in the
three MSB locations of the output serial data (Table 4).
The CH_ OUT data is delayed by one read cycle. In
other words, each CH_ OUT bit is the result of the com-
parison made against the CH DAC voltage programmed
during the previous serial-write operation.
An analog-to-digital (A/D) conversion can be performed
on a channel by using the system software to step
through a successive-approximation routine or, if the
input is partially known, by setting the CH DAC to a
voltage near the estimated point and checking succes-
sive CH_ OUT bits.
10 ______________________________________________________________________________________

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