HEF4046BT(2016) データシートの表示（PDF） - NXP Semiconductors.

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HEF4046BT
(Rev.:2016)

Phase-locked loop

NXP Semiconductors. 

Nexperia

HEF4046B

Phase-locked loop

7. Limiting values

Table 3. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol

Parameter

Conditions

VDD

IIK

VI

IOK

II/O

IDD

Tstg

Tamb

Ptot

P

supply voltage

input clamping current

input voltage

output clamping current

input/output current

supply current

storage temperature

ambient temperature

total power dissipation

power dissipation

VI < 0.5 V or VI > VDD + 0.5 V

VO < 0.5 V or VO > VDD + 0.5 V

SO16 package

[1]

per output

[1] For SO16 package: Ptot derates linearly with 8 mW/K above 70 C.

Min

0.5

-

0.5

-

-

-

65

40

-

-

8. Recommended operating conditions

Max

Unit

+18

V

10

mA

VDD + 0.5 V

10

mA

10

mA

50

mA

+150 C

+85

C

500

mW

100

mW

Table 4.

Symbol

VDD

VI

Tamb

t/V

Recommended operating conditions

Parameter

Conditions

supply voltage

as fixed oscillator only

phase-locked loop operation

input voltage

ambient temperature

in free air

input transition rise and fall rate for INH input

VDD = 5 V

VDD = 10 V

VDD = 15 V

Min Typ

3

-

3

-

5

-

0

-

40

-

Max Unit

15 V

15 V

15 V

VDD V

+85 C

-

-

3.75 s/V

-

-

0.5 s/V

-

-

0.08 s/V

HEF4046B

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 6 — 24 March 2016

© Nexperia B.V. 2017. All rights reserved

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