HEF4046B データシートの表示（PDF） - NXP Semiconductors.
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HEF4046B Datasheet PDF : 20 Pages
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NXP Semiconductors
HEF4046B
Phase-locked loop
Figure 6 shows the state diagram for phase comparator 2. Each circle represents a state
of the comparator. The number at the top, inside each circle, represents the state of the
comparator, while the logic state of the signal and comparator inputs are represented by a
‘0’ for a logic LOW or a ‘1’ for a logic HIGH, and they are shown in the left and right bottom
of each circle.
The transitions from one to another result from either a logic change at the signal input (S
representing SIG_IN) or the comparator input (C representing COMP_IN). A positive-
going and a negative-going transition are shown by an arrow pointing up or down
respectively.
The state diagram assumes, that only one transition on either the signal input or
comparator input occurs at any instant.
• States 3, 5, 9 and 11 represent the output condition when the p-type driver is ON.
• States 2, 4, 10 and 12 determine the condition when the n-type driver is ON.
• States 1, 6, 7 and 8 represent the condition when the output is in its high-impedance
OFF state; i.e. both p and n-type drivers are OFF, and the PCP_OUT output is HIGH.
The condition at output PCP_OUT for all other states is LOW.
S
S
8
10
C
C
4
00
C
C
2
01
S
C
S
S
C
10
11
C
12
10
n-type driver ON
1
00
6
11
S
3
10
C
S
S
5
00
S
C
C
11
01
S
9
11
S
p-type driver ON
C
C
7
01
S
n and p-type
drivers are OFF
n
00
logic state of
signal input (pin 14)
state number of
the comparator
logic state of
comparator input (pin 3)
Fig 6.
S : 0 to 1 transition at the signal input SIG_IN.
C : 1 to 0 transition at the comparator input COMP_IN.
State diagram for comparator 2
HEF4046B
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 18 November 2011
001aae631
© NXP B.V. 2011. All rights reserved.
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