HEF4046B データシートの表示（PDF） - NXP Semiconductors.

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HEF4046B

Phase-locked loop

NXP Semiconductors. 

NXP Semiconductors

HEF4046B

Phase-locked loop

7. Limiting values

Table 3. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol

Parameter

Conditions

VDD

IIK

VI

IOK

II/O

IDD

Tstg

Tamb

Ptot

supply voltage

input clamping current

input voltage

output clamping current

input/output current

supply current

storage temperature

ambient temperature

total power dissipation

VI < 0.5 V or VI > VDD + 0.5 V

VO < 0.5 V or VO > VDD + 0.5 V

DIP16 package

SO16 package

P

power dissipation

per output

[1] For DIP16 package: Ptot derates linearly with 12 mW/K above 70 C.

[2] For SO16 package: Ptot derates linearly with 8 mW/K above 70 C.

Min

0.5

-

0.5

-

-

-

65

40

[1] -

[2] -

-

8. Recommended operating conditions

Max

Unit

+18

V

10

mA

VDD + 0.5 V

10

mA

10

mA

50

mA

+150

C

+85

C

750

mW

500

mW

100

mW

Table 4.

Symbol

VDD

VI

Tamb

t/V

Recommended operating conditions

Parameter

Conditions

supply voltage

as fixed oscillator only

phase-locked loop operation

input voltage

ambient temperature

in free air

input transition rise and fall rate for INH input

VDD = 5 V

VDD = 10 V

VDD = 15 V

Min Typ Max

3

-

15

3

-

15

5

-

15

0

-

VDD

40 -

+85

Unit

V

V

V

V

C

-

-

3.75

s/V

-

-

0.5

s/V

-

-

0.08

s/V

HEF4046B

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 5 — 18 November 2011

© NXP B.V. 2011. All rights reserved.

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