QG82945GMESLA9H データシートの表示（PDF） - Intel
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QG82945GMESLA9H Datasheet PDF : 319 Pages
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3.4.2.2 DMI Configuration Accesses ............................................... 57
3.5 I/O Mapped Registers .......................................................................................... 57
3.5.1 CONFIG_ADDRESS—Configuration Address Register ...................... 58
3.5.2 CONFIG_DATA—Configuration Data Register .................................... 59
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Host Bridge/DRAM Controller Registers (D0:F0) ............................................................. 61
4.1 Device 0 Configuration Register Details .............................................................. 63
4.1.1 VID—Vendor Identification (D0:F0) ...................................................... 63
4.1.2 DID—Device Identification (D0:F0) ...................................................... 63
4.1.3 PCICMD—PCI Command (D0:F0) ....................................................... 64
4.1.4 PCISTS—PCI Status (D0:F0) ............................................................... 65
4.1.5 RID—Revision Identification (D0:F0).................................................... 66
4.1.6 CC—Class Code (D0:F0) ..................................................................... 66
4.1.7 MLT—Master Latency Timer (D0:F0) ................................................... 67
4.1.8 HDR—Header Type (D0:F0) ................................................................ 67
4.1.9 SVID—Subsystem Vendor Identification (D0:F0)................................. 67
4.1.10 SID—Subsystem Identification (D0:F0) ................................................ 68
4.1.11 CAPPTR—Capabilities Pointer (D0:F0) ............................................... 68
4.1.12 EPBAR—Egress Port Base Address (D0:F0) ...................................... 69
4.1.13 MCHBAR—(G)MCH Memory Mapped Register Range Base Address
(D0:F0) .................................................................................................. 70
4.1.14 PCIEXBAR—PCI Express* Register Range Base Address (D0:F0)
(Intel® 82945G/82945GC/82945P/82945PL (G)MCH Only)................. 71
4.1.15 DMIBAR—Root Complex Register Range Base Address (D0:F0) ...... 73
4.1.16 GGC—GMCH Graphics Control Register (D0:F0) (Intel®
82945G/82945GC/82945GZ GMCH Only).......................................... 74
4.1.17 DEVEN—Device Enable (D0:F0) ......................................................... 75
4.1.18 PAM0—Programmable Attribute Map 0 (D0:F0) .................................. 76
4.1.19 PAM1—Programmable Attribute Map 1 (D0:F0) .................................. 77
4.1.20 PAM2—Programmable Attribute Map 2 (D0:F0) .................................. 78
4.1.21 PAM3—Programmable Attribute Map 3 (D0:F0) .................................. 79
4.1.22 PAM4—Programmable Attribute Map 4 (D0:F0) .................................. 80
4.1.23 PAM5—Programmable Attribute Map 5 (D0:F0) .................................. 81
4.1.24 PAM6—Programmable Attribute Map 6 (D0:F0) .................................. 82
4.1.25 LAC—Legacy Access Control (D0:F0) ................................................. 83
4.1.26 TOLUD—Top of Low Usable DRAM (D0:F0) ....................................... 84
4.1.27 SMRAM—System Management RAM Control (D0:F0)........................ 85
4.1.28 ESMRAMC—Extended System Management RAM Control (D0:F0) .. 86
4.1.29 ERRSTS—Error Status (D0:F0) ........................................................... 87
4.1.30 ERRCMD—Error Command (D0:F0) ................................................... 88
4.1.31 SKPD—Scratchpad Data (D0:F0) ........................................................ 89
4.1.32 CAPID0—Capability Identifier (D0:F0) ................................................. 89
4.2 MCHBAR Register ............................................................................................... 90
4.2.1 C0DRB0—Channel A DRAM Rank Boundary Address 0 .................... 91
4.2.2 C0DRB1—Channel A DRAM Rank Boundary Address 1 .................... 93
4.2.3 C0DRB2—Channel A DRAM Rank Boundary Address 2 .................... 93
4.2.4 C0DRB3—Channel A DRAM Rank Boundary Address 3 .................... 93
4.2.5 C0DRA0—Channel A DRAM Rank 0,1 Attribute ................................. 94
4.2.6 C0DRA2—Channel A DRAM Rank 2,3 Attribute ................................. 94
4.2.7 C0DCLKDIS—Channel A DRAM Clock Disable .................................. 95
4.2.8 C0BNKARC—Channel A DRAM Bank Architecture ............................ 96
4.2.9 C0DRT1—Channel A DRAM Timing Register ..................................... 97
4.2.10 C0DRC0—Channel A DRAM Controller Mode 0 ................................. 98
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Intel® 82945G/82945GZ/82945GC GMCH and 82945P/82945PL MCH Datasheet
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