QG82945GMESLA9H データシートの表示（PDF） - Intel
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QG82945GMESLA9H Datasheet PDF : 319 Pages
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9.4.5
9.4.6
9.4.7
9.4.8
9.4.9
9.4.10
9.4.11
9.4.12
SMM Space Decode and Transaction Handling ................................ 219
Processor WB Transaction to an Enabled SMM Address Space ...... 219
SMM Access through GTT TLB (Intel® 82945G/82945GC/82945GZ
GMCH Only) ....................................................................................... 219
Memory Shadowing ............................................................................ 219
I/O Address Space.............................................................................. 220
PCI Express* I/O Address Mapping ................................................... 220
(G)MCH Decode Rules and Cross-Bridge Address Mapping ............ 220
Legacy VGA and I/O Range Decode Rules ....................................... 221
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Functional Description .................................................................................................... 223
10.1 Host Interface ..................................................................................................... 223
10.1.1 FSB IOQ Depth................................................................................... 223
10.1.2 FSB OOQ Depth ................................................................................. 223
10.1.3 FSB GTL+ Termination....................................................................... 223
10.1.4 FSB Dynamic Bus Inversion ............................................................... 223
10.1.4.1 APIC Cluster Mode Support .............................................. 224
10.2 System Memory Controller ................................................................................. 224
10.2.1 System Memory Configuration Registers Overview ........................... 226
10.2.2 DRAM Technologies and Organization .............................................. 226
10.2.2.1 Rules for Populating DIMM Slots ...................................... 228
10.2.2.2 System Memory Supported Configurations ...................... 229
10.2.2.3 Main Memory DRAM Address Translation and Decoding 229
10.2.3 DRAM Clock Generation .................................................................... 232
10.2.4 Suspend to RAM and Resume ........................................................... 232
10.2.5 DDR2 On Die Termination.................................................................. 232
10.3 PCI Express* (Intel® 82945G/82945GC/ 82945P/82945PL (G)MCH Only)...... 233
10.3.1 Transaction Layer ............................................................................... 233
10.3.2 Data Link Layer................................................................................... 233
10.3.3 Physical Layer..................................................................................... 233
10.4 Intel® Serial Digital Video Output (SDVO) (Intel® 82945G/82945GC/82945GZ
GMCH Only) ....................................................................................................... 234
10.4.1
10.4.2
10.4.3
Intel® SDVO Capabilities..................................................................... 234
Intel® SDVO Modes ............................................................................ 235
PCI Express* and Internal Graphics Simultaneous Operation (Intel®
82945G/82945GC GMCH Only) ......................................................... 236
10.4.3.1 Standard PCI Express* Cards and Internal Graphics ....... 236
10.4.3.2 ADD2+ Cards (Concurrent SDVO and PCI Express*) ...... 236
10.5 Integrated Graphics Device (Intel® 82945G/82945GC/82945GZ GMCH Only) 239
10.5.1 3D Graphics Pipeline .......................................................................... 239
10.5.2 3D Engine ........................................................................................... 240
10.5.3 4X Faster Setup Engine...................................................................... 241
10.5.3.1 3D Primitives and Data Formats Support.......................... 241
10.5.3.2 Pixel Accurate “Fast” Scissoring and Clipping Operation . 241
10.5.3.3 Depth Bias ......................................................................... 241
10.5.3.4 Backface Culling................................................................ 242
10.5.3.5 Scan Converter.................................................................. 242
10.5.3.6 Pixel Rasterization Rules .................................................. 242
10.5.3.7 Pixel Pipeline ..................................................................... 242
10.5.3.8 Texture Samplers .............................................................. 242
10.5.3.9 2D Functionality................................................................. 242
10.5.4 Texture Engine.................................................................................... 243
Intel® 82945G/82945G/82945GC GMCH and 82945P/82945PL MCH Datasheet
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