MX25L6406E データシートの表示（PDF） - Macronix International

部品番号

コンポーネント説明

メーカー

MX25L6406E

64M-BIT [x 1 / x 2] CMOS SERIAL FLASH

Macronix International 

MX25L6406E

8. DATA PROTECTION

During power transition, there may be some false system level signals which result in inadvertent erasure or

programming. The device is designed to protect itself from these accidental write cycles.

The state machine will be reset as standby mode automatically during power up. In addition, the control register

architecture of the device constrains that the memory contents can only be changed after specific command

sequences have completed successfully.

In the following, there are several features to protect the system from the accidental write cycles during VCC power-

up and power-down or from system noise.

• Valid command length checking: The command length will be checked whether it is at byte base and completed

on byte boundary.

• Write Enable (WREN) command: WREN command is required to set the Write Enable Latch bit (WEL) before

other command to change data. The WEL bit will return to reset stage under following situation:

- Power-up

- Write Disable (WRDI) command completion

- Write Status Register (WRSR) command completion

- Page Program (PP) command completion

- Sector Erase (SE) command completion

- Block Erase (BE) command completion

- Chip Erase (CE) command completion

• Deep Power Down Mode: By entering deep power down mode, the flash device also is under protected from

writing all commands except Release from deep power down mode command (RDP) and Read Electronic Sig-

nature command (RES).

• Advanced Security Features: there are some protection and security features which protect content from inad-

vertent write and hostile access.

I. Block lock protection

- The Software Protected Mode (SPM):

MX25L6406E: use (BP3, BP2, BP1, BP0) bits to allow part of memory to be protected as read only. The proect-

ed area definition is shown as "Table 2. Protected Area Sizes", the protected areas are more flexible which may

protect various area by setting value of BP0-BP3 bits.

- The Hardware Proteced Mode (HPM) uses WP# to protect the MX25L6406E: BP3-BP0 bits and SRWD bit.

P/N: PM1577

REV. 1.8, NOV. 12, 2013

11

Share Link: