MX25L6406E(2010) データシートの表示（PDF） - Macronix International

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MX25L6406E
(Rev.:2010)

64M-BIT [x 1 / x 2] CMOS SERIAL FLASH

Macronix International 

MX25L6406E

POWER-ON STATE.................................................................................................................................................... 24

ELECTRICAL SPECIFICATIONS.............................................................................................................................. 25

ABSOLUTE MAXIMUM RATINGS...................................................................................................................... 25

Figure 3.Maximum Negative Overshoot Waveform............................................................................................ 25

CAPACITANCE TA = 25°C, f = 1.0 MHz............................................................................................................. 25

Figure 4. Maximum Positive Overshoot Waveform............................................................................................. 25

Figure 5. INPUT TEST WAVEFORMS AND MEASUREMENT LEVEL.............................................................. 26

Figure 6. OUTPUT LOADING............................................................................................................................ 26

Table 8. DC CHARACTERISTICS...................................................................................................................... 27

Table 9. AC CHARACTERISTICS....................................................................................................................... 28

Timing Analysis......................................................................................................................................................... 29

Figure 7. Serial Input Timing............................................................................................................................... 29

Figure 8. Output Timing...................................................................................................................................... 29

Figure 9. Hold Timing.......................................................................................................................................... 30

Figure 10. WP# Disable Setup and Hold Timing during WRSR when SRWD=1................................................ 30

Figure 11. Write Enable (WREN) Sequence (Command 06).............................................................................. 31

Figure 12. Write Disable (WRDI) Sequence (Command 04).............................................................................. 31

Figure 13. Read Status Register (RDSR) Sequence (Command 05)................................................................. 32

Figure 14. Write Status Register (WRSR) Sequence (Command 01)............................................................... 32

Figure 15. Read Data Bytes (READ) Sequence (Command 03)....................................................................... 32

Figure 16. Read at Higher Speed (FAST_READ) Sequence (Command 0B)................................................... 33

Figure 17. Dual Output Read Mode Sequence (Command 3B)......................................................................... 34

Figure 18. Sector Erase (SE) Sequence (Command 20)................................................................................... 34

Figure 19. Block Erase (BE) Sequence (Command 52 or D8).......................................................................... 34

Figure 20. Chip Erase (CE) Sequence (Command 60 or C7)............................................................................ 35

Figure 21. Page Program (PP) Sequence (Command 02)................................................................................ 35

Figure 22. Deep Power-down (DP) Sequence (Command B9)......................................................................... 36

Figure 23. Release from Deep Power-down (RDP) Sequence (Command AB)................................................ 36

Figure 24. Release from Deep Power-down and Read Electronic Signature (RES) Sequence (Command AB).36

Figure 25. Read Identification (RDID) Sequence (Command 9F)...................................................................... 37

Figure 26. Read Electronic Manufacturer & Device ID (REMS) Sequence (Command 90).............................. 37

Figure 27. Read Security Register (RDSCUR) Sequence (Command 2B)........................................................ 38

Figure 28. Write Security Register (WRSCUR) Sequence (Command 2F)........................................................ 38

Figure 29. Program/ Erase flow with read array data......................................................................................... 39

Figure 30. Power-up Timing................................................................................................................................ 40

Table 10. Power-Up Timing ................................................................................................................................ 40

OPERATING CONDITIONS....................................................................................................................................... 41

Figure 31. AC Timing at Device Power-Up......................................................................................................... 41

Figure 32. Power-Down Sequence..................................................................................................................... 42

P/N: PM1577

REV. 1.1, NOV. 17, 2010

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