PCA9617A データシートの表示（PDF） - ON Semiconductor

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PCA9617A

Level-Translating Fm+ I2C-Bus Repeater

ON Semiconductor 

PCA9617A

FUNCTIONAL DESCRIPTION

Please refer to Figure 1 ”Block Diagram of PCA9617A”.

The PCA9617A enables I2C−bus or SMBus translation

down to VCC(A) as low as 0.8 V without degradation of

system performance. The PCA9617A contains two

bidirectional open−drain buffers specifically designed to

support up−translation/down−translation between the low

voltage (as low as 0.8 V) and a 2.5 V, 3.3 V or 5 V I2C−bus

or SMBus. All inputs and I/Os are overvoltage tolerant to

5.5 V even when the device is unpowered (VCC(B) and/or

VCC(A) = 0 V). The PCA9617A includes a power−up circuit

that keeps the output drivers turned off until VCC(B) is above

2.2 V and until after the internal reference circuits have

settled in ~400 ms, and the VCC(A) is above 0.8 V. VCC(B) and

VCC(A) can be applied in any sequence at power−up. After

power−up and with the enable (EN) HIGH, a LOW level on

port A (below 0.3VCC(A)) turns the corresponding port B

driver (either SDA or SCL) on and drives port B down to

about 0.55 V. When port A rises above 0.3VCC(A), the port

B pull−down driver is turned off and the external pull−up

resistor pulls the pin HIGH. When port B falls first and goes

below 0.4 V, the port A driver is turned on and port A pulls

down to ~0 V. The port A pull−down is not enabled unless

the port B voltage goes below 0.4 V. If the port B low voltage

goes below 0.4 V, the port B pull−down driver is enabled and

port B will only be able to rise to 0.55 V until port A rises

above 0.3VCC(A), then port B will continue to rise being

pulled up by the external pull−up resistor. The VCC(A) is only

used to provide the 0.35VCC(A) reference to the port A input

comparators and for the power good detect circuit. The

PCA9617A includes a VCC(A) overvoltage disable that turns

the channel off if 0.4VCC(A) + 0.8 V > VCC(B). The

PCA9617A logic and all I/Os are powered by the VCC(B)

pin.

Enable Pin (EN)

The EN pin is active HIGH with thresholds referenced to

VCC(B) and an internal pull−up to VCC(B) that maintains the

device active unless the user selects to disable the repeater

to isolate a badly behaved slave on power−up until after the

system power−up reset. It should never change state during

an I2C−bus operation because disabling during a bus

operation will hang the bus and enabling part way through

a bus cycle could confuse the I2C−bus parts being enabled.

The enable does not switch the internal reference circuits so

the ~400 ms delay is only seen when VCC(B) comes up.

The enable pin should only change state when the global

bus and the repeater port are in an idle state to prevent system

failures.

I2C−Bus Systems

As with the standard I2C−bus system, pull−up resistors are

required to provide the logic HIGH levels on the buffered

bus (standard open−collector configuration of the I2C−bus).

The size of these pull−up resistors depends on the system,

but each side of the repeater must have a pull−up resistor.

This part is designed to work with Standard mode,

Fast−mode and Fast−mode Plus I2C−bus devices in addition

to SMBus devices. Standard mode and Fast−mode I2C−bus

devices only specify 3 mA output drive; this limits the

termination current to 3 mA in a generic I2C−bus system

where Standard−mode devices, Fast−mode devices and

multiple masters are possible. When only Fast−mode Plus

devices are used with 30 mA at 5 V drive strength, then

lower value pull−up resistors can be used. The B−side RC

should not be less than 67.5 ns because shorter RCs increase

the turnaround bounce when the B−side transitions from

being externally driven to pulled down by its offset buffer.

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