HEF4051B-Q100 データシートの表示（PDF） - NXP Semiconductors.
部品番号
コンポーネント説明
メーカー
HEF4051B-Q100 Datasheet PDF : 21 Pages
| |||
Nexperia
HEF4051B-Q100
8-channel analog multiplexer/demultiplexer
7. Functional description
7.1 Function table
Table 3. Function table[1]
Input
E
S3
S2
S1
L
L
L
L
L
L
L
H
L
L
H
L
L
L
H
H
L
H
L
L
L
H
L
H
L
H
H
L
L
H
H
H
H
X
X
X
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care.
8. Limiting values
Channel ON
Y0 to Z
Y1 to Z
Y2 to Z
Y3 to Z
Y4 to Z
Y5 to Z
Y6 to Z
Y7 to Z
switches off
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to VSS = 0 V (ground).
Symbol
Parameter
Conditions
Min
Max
Unit
VDD
VEE
IIK
VI
II/O
IDD
Tstg
Tamb
Ptot
supply voltage
supply voltage
input clamping current
input voltage
input/output current
supply current
storage temperature
ambient temperature
total power dissipation
referenced to VDD
pins Sn and E;
VI < 0.5 V or VI > VDD + 0.5 V
Tamb = 40 C to +125 C
SO16 and TSSOP16
package
0.5
[1] 18
-
0.5
-
-
65
40
[2] -
+18
V
+0.5
V
10
mA
VDD + 0.5 V
10
mA
50
mA
+150
C
+125
C
500
mW
P
power dissipation
per output
-
100
mW
[1] To avoid drawing VDD current out of terminal Z, when switch current flows into terminals Y, the voltage drop across the bidirectional
switch must not exceed 0.4 V. If the switch current flows into terminal Z, no VDD current will flow out of terminals Y, and in this case there
is no limit for the voltage drop across the switch, but the voltages at Y and Z may not exceed VDD or VEE.
[2] For SO16 package: Ptot derates linearly with 8 mW/K above 70 C.
For TSSOP16 package: Ptot derates linearly with 5.5 mW/K above 60 C.
HEF4051B_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 11 September 2014
© Nexperia B.V. 2017. All rights reserved
6 of 21
Share Link: 