STLC5460 データシートの表示（PDF） - STMicroelectronics
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STLC5460 Datasheet PDF : 54 Pages
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STLC5460
PIN DEFINITIONS AND FUNCTIONS (continued)
Symbol Pin n PLCC
AS/ALE
31
Type
I
INT
32
DCL
33
FSC
34
VDD2
35
VSS2
36
DIN1
37
DIN0
38
A3
39
OD
0
O
I
I
I
I
I (**)
DOUT0
40
DOUT1
41
PO
42
NRDY/N
43
WAIT
RES
44
(*): (I) Input
(O) Output
(IO) In/Output
(OD) Open Drain
(**): With Pull up resistance.
O
O
I (**)
OD
I
Function
Multiplexed A/D mode:
used to latch the address from ADn
Non Multiplexed A/D Mode:
This pin at VSS indicates Intel like interfaces
This pin at VDD indicates Motorola like interfaces.
Interrupt line, active low.
Data clock output.
Frame synchronization output.
Power supply : 5V
Ground.
GCI Data input 1
GCI Data input 0
Non Multiplexed Mode:
this input interfaces to the system’s address bus to select an internal
register for a read or write access.
Multiplexed Mode:
A3 at VDD, DS/NRD signal provided by the system is not inverted by the
circuit
A3 at VSS, DS/NRD signal provided by the system isinverted by the circuit
GCI Data Output 0
GCI Data Output 1
P0 at VSS: variable access mode
P0 at VDD: fixed access mode
If P0 at VSS:
Intel like mode: this pin delivers NRDY
Motorola mode: this pin delivers NWAIT
Reset. A logical high on this input forces the STLC5460 into the reset state
Figure 1: GCI and PCM Interfaces.
4/54
DCL
FSC
DOUT0
DIN0
DOUT1
DIN1
CLOCKS
PCM0
MUX0/GCI0
MUX1/GCI1
PCM1
PCM2
PCM3
LCIC
PDC
PFS
RxD0
TxD0
TSC0
RxD1
TxD1
TSC1
RxD2
TxD2
TSC2
RxD3
TxD3
TSC3
MICROPROCESSOR INTERFACE
D94TL159A
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