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STK551U362AGEVB データシートの表示(PDF) - ON Semiconductor

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STK551U362AGEVB
ON-Semiconductor
ON Semiconductor ON-Semiconductor
STK551U362AGEVB Datasheet PDF : 16 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
Logic Timing Chart
HIN1,2,3
ON
OFF
LIN1,2,3
STK551U362A-E
VBS undervoltage protection reset signal
VDD
VDD undervoltage protection reset voltage
*2
VB1,2,3
*3VBS undervoltage protection reset voltage
*4
-------------------------------------------------------ISD operation current level-------------------------------------------------------
-terminal
(BUS line)
Current
FAULT terminal
Voltage
(at pulled-up)
ON
*1
Upper
U, V, W
OFF
*1
Lower
U ,V, W
Automatically reset after protection
(18ms to 80ms)
Notes
Fig. 7
*1 : Diagram shows the prevention of shoot-through via control logic. More dead time to account for switching delay needs to be
added externally.
*2 : When VDD decreases all gate output signals will go low and cut off all of 6 IGBT outputs. part. When VDD rises the operation
will resume immediately.
*3 : When the upper side gate voltage at VB1, VB2 and VB3 drops only, the corresponding upper side output is turned off. The
outputs return to normal operation immediately after the upper side gat voltage rises.
*4 : In case of over current detection, all IGBT’s are turned off and the FAULT output is asserted. Normal operation resumes in 18 to
80ms after the over current condition is removed.
No.A2210-8/15

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