SAA4945H データシートの表示（PDF） - Philips Electronics

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SAA4945H

LIne MEmory noise Reduction IC (LIMERIC)

Philips Electronics 

Philips Semiconductors

LIne MEmory noise Reduction IC

(LIMERIC)

Preliminary specification

SAA4945H

Table 9 Test settings

TST2

0

X(1)

1

X(1)

TST1

0

1

X(1)

X(1)

Note

1. X = don’t care.

TST0

0

X(1)

X(1)

1

application mode

test mode

test mode

test mode

MODE

SNDA, SNCL AND VRST (PINS 2, 3 AND 4)

• Serial interface signals

• SNERT bus protocol (Synchronous No parity 8-bit receiver and Transmission bus)

• SNDA is a bidirectional signal with 8-bit wide data and address (LSB first)

• Serial interface signals converted (internally) to system clock domain. To avoid set-up violations these signals are

clocked two times by the system clock before further processing is performed.

• Synchronization of serial address (every even byte) and data (every odd byte) by VRST.

handbook, full pagewidth

SNCL

SNDA

(receiver

mode)

SNDA

(transmitter

mode)

Tcy(SNCL)

tsu(i)(D)

th(D)

LSB

data

valid

data

valid

th(Q)

data

valid

data

valid

td(D)

data

valid

data

valid

Fig.5 Timing diagram of serial interface.

Table 10 Timing characteristics (see Fig.5)

SYMBOL

tcy(SNCL)

tsu(i)(D)

th(D)

th(Q)

td(D)

PARAMETER

SNCL cycle time

input set-up time

input hold time

output data hold time

output data delay time

MIN.

1

90

50

0

−

MAX.

−

−

−

−

700

data

valid

MGK173

UNIT

µs

ns

ns

ns

ns

1997 Jun 10

10

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