GBE-PCS-PM-U1 データシートの表示（PDF） - Lattice Semiconductor

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GBE-PCS-PM-U1

Gigabit Ethernet PCS IP Core for LatticeECP2M

Lattice Semiconductor 

Lattice Semiconductor

Gigabit Ethernet PCS IP Core

for LatticeECP2M

Synthesizing and Implementing the Core in a Top-Level Design

The GbE PCS IP core itself is synthesized and is provided in NGO format when the core is generated. You may

synthesize the core in your own top-level design by instantiating the core in your top-level as described above in the

“Instantiating the Core” section and then synthesizing the entire design with either Synplicity® or Precision® RTL.

As described previously, two example RTL top-level configurations supporting GbE PCS core top-level synthesis

and implementation are provided in \<project_dir>\gbe_pcs_eval\<username>\src\rtl\top\<tech-

nology>.

The top-level file top_gbe_pcs_core_only.v provided in \<project_dir>\gbe_pcs_eval\<user-

name>\src\rtl\top supports the ability to implement just the GBE_PCS core. This design is intended only to

provide an accurate indication of the device utilization associated with the core itself and should not be used as an

actual implementation example.

The top-level file top.v is a GbE Physical Layer Reference design \<project_dir>\gbe_pcs_eval\<user-

name>\src\rtl\top supports the ability to instantiate, simulate, map, place and route the GBE_PCS IP core in

a complete example design. A complete description of this design is given in an appendix to this document. Note

that implementation of the reference evaluation configuration is specifically targeted to a LatticeECP2M

LFE2M35E-6F672C device.

Push-button implementation of both top-level configurations is supported via the ispLEVER project files, <user-

name>_reference_eval.syn and <username>_core_only_eval.syn. These files are located in

<project_dir>\ten_gbemac_test\ten_gbemac_eval\<username>\impl\<configuration>.

To use these project files:

1. Select Open Project under the File tab in ispLEVER.

2. Browse to the \<project_dir\gbe_pcs_eval\<username>\impl directory and select either the

\core_only or \reference directory in the Open Project dialog box.

3. Select and open either <username>_reference_eval.syn or username>_core_only_eval.syn. At this

point, all of the files needed to support top-level synthesis and implementation will be imported to the project.

4. Select the device top-level entry in the left-hand GUI window.

5. Implement the complete design via the standard ispLEVER GUI flow.

Hardware Evaluation

Lattice’s IP hardware evaluation capability makes it possible to create versions of IP cores that operate in hardware

for a limited period of time (approximately four hours) without requiring the purchase on an IP license. The hard-

ware evaluation capability may be enabled/disabled in the Properties menu of the Build Database setup in

ispLEVER Project Navigator. It is enabled by default.

References

• ispLEVER Software User Manual

• ispLeverCORE™ IP Module Evaluation Tutorial available on the Lattice website at www.latticesemi.com

Technical Support Assistance

Hotline: 1-800-LATTICE (North America)

+1-503-268-8001 (Outside North America)

e-mail: techsupport@latticesemi.com

Internet: www.latticesemi.com

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