NCP5425DBR2G データシートの表示（PDF） - ON Semiconductor
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NCP5425DBR2G Datasheet PDF : 22 Pages
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NCP5425
ELECTRICAL CHARACTERISTICS (0°C < TJ < 125°C; ROSC = 30.9 k, CCOMP1,2 = 0.1 mF, 4.75 V < VCC < 13.2 V;
10.8 V < BST < 20 V, CGATE(H)1,2 = CGATE(L)1,2 = 1.0 nF; unless otherwise specified.)
Characteristic
Test Condition
Min
Typ
Max
ERROR AMPLIFIER
VFB1 Input Bias Current
VFB2, VREF2 Input Bias Current
Common Mode Input Voltage Range
VFB1 = 0 V
VFB2, VREF2 = 0.8 V
−
−
0.1
1.0
−
0.1
1.0
0.3
−
1.0
COMP1(2) Source Current
COMP1(2) Sink Current
Reference Voltage
COMP1 Max Voltage
COMP2 Max Voltage, Mode Floating
COMP2 Max Voltage, Mode = 0
COMP1(2) Min Voltage
Open Loop Gain
COMP1(2) = 1.2 V to 2.5 V; VFB1(2) = 0.6 V
COMP1(2) = 1.2 V; VFB1(2) = 1.0 V
COMP1 = VFB1
VFB1(2) = 0.6 V
VFB1(2) = 0.6 V
VFB1(2) = 0.6 V
VFB1(2) = 1.2 V
15
15
0.792
−
3.0
−
−
−
30
30
0.800
2.0
3.1
2.0
0.10
95
60
60
0.808
2.1
−
2.1
0.20
−
Unity Gain Bandwidth
−
40
−
PSRR @ 1.0 kHz
−
70
−
Transconductance
−
−
32
−
Output Impedance
−
−
2.5
−
GATE(H) AND GATE(L)
High Voltage (AC)
VCC − GATE(L)1,2
BST − GATE(H)1,2 (Note 2)
−
0
0.5
Low Voltage (AC)
GATE(L)1,2 or GATE(H)1,2 (Note 2)
−
0
0.5
Rise Time
1.0 V < GATE(L)1,2 < VCC − 1.0 V
1.0 V < GATE(H)1,2 < BST − 1.0 V
−
25
80
Fall Time
VCC − 1.0 > GATE(L)1,2 > 1.0 V
BST − 1.0 > GATE(H)1,2 > 1.0 V
−
25
80
GATE(H) to GATE(L) Delay
GATE(H)1,2 < 2.0 V
GATE(L)1,2 > 2.0 V
20
40
80
GATE(L) to GATE(H) Delay
GATE(L)1,2 < 2.0 V
GATE(H)1,2 > 2.0 V
20
40
80
GATE(H)1(2) and GATE(L)1(2) Pull−Down
Resistance to GND (Note 2)
50
125
280
PWM COMPARATOR
Propagation Delay
PWM Comparator Offset
COMP1(2) = 1.0 V
VFB1(2) = 0 to 1.2 V (Note 2)
VFB1(2) = 0 V; Increase COMP1(2) until
GATE(H)1(2) starts switching
−
200
300
0.20 0.30 0.45
Artificial Ramp
Duty Cycle = 50%
55
95
150
Minimum Pulse Width
(Note 2)
2. Guaranteed by design, not 100% tested in production.
−
80
130
Unit
mA
mA
V
mA
mA
V
V
V
dB
kHz
dB
mmho
MW
V
V
ns
ns
ns
ns
kW
ns
V
mV
ns
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