LNBS21(2002) データシートの表示（PDF） - STMicroelectronics

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LNBS21
(Rev.:2002)

LNB SUPPLY AND CONTROL IC WITH STEP-UP CONVERTER AND I2C INTERFACE

STMicroelectronics 

LNBS21

TYPICAL APPLICATION CIRCUIT

Schottky

diode

STPS3L40S

or 1N5821

L1=22µH

Vin

12V

C2

220µF

IC1

C3

470nF

Ceramic

Vup

D1 1N4001

LT1

LT2

MOSFET

STN4NF03L

Rsc

0.05Ω

C1

220µF

C4

470nF

Ceramic

Gate

Sense

LNBS21

Vout

C8

10nF

DETIN(*)

Vcc

DSQIN(*)

SCL

SDA

Byp

GND

EXTM

ADDRESS

DSQOUT

Master STB

C7

10nF

270µH

D2

BAT43

15 ohm

(**) see note

C6

10nF

C5

470nF

0<Vaddr<VByp

to LNB

(*) Set to GND if not used

(**) filter to be used according to EUTELSAT reccomendation to implement the DiSEqCTM 2.0, not needed if bidirectional DiSEqCTM 2.0 is

not implemented (see DiSEqC implementation note)

I2C BUS INTERFACE

Data transmission from main µP to the LNBS21

and viceversa takes place through the 2 wires I2C

bus interface, consisting of the two lines SDA and

SCL (pull-up resistors to positive supply voltage

must be externally connected).

DATA VALIDITY

As shown in fig. 1, the data on the SDA line must

be stable during the high period of the clock. The

HIGH and LOW state of the data line can only

change when the clock signal on the SCL line is

LOW.

START AND STOP CONDITIONS

As shown in fig.2 a start condition is a HIGH to

LOW transition of the SDA line while SCL is HIGH.

The stop condition is a LOW to HIGH transition of

the SDA line while SCL is HIGH. A STOP

condi-tions must be sent before each START

condition.

BYTE FORMAT

Every byte transferred to the SDA line must

contain 8 bits. Each byte must be followed by an

ac-knowledge bit. The MSB is transferred first.

ACKNOWLEDGE

The master (µP) puts a resistive HIGH level on the

SDA line during the acknowledge clock pulse (see

fig. 3). The peripheral (LNBS21) that

acknowledges has to pull-down (LOW) the SDA

line during the acknowledge clock pulse, so that

the SDA line is stable LOW during this clock pulse.

The peripheral which has been addressed has to

generate an acknowledge after the reception of

each byte, other-wise the SDA line remains at the

HIGH level during the ninth clock pulse time. In

this case the master transmitter can generate the

STOP information in order to abort the transfer.

The LNBS21 won't gen-erate the acknowledge if

the Vcc supply is below the Undervoltage Lockout

threshold (6.7V typ.).

TRANSMISSION WITHOUT ACKNOWLEDGE

Avoiding to detect the acknowledge of the

LNBS21, the µP can use a simpler transmission:

simply it waits one clock without checking the

slave acknowledging, and sends the new data.

This approach of course is less protected from

misworking and decreases the noise immunity.

5/19

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