74LV595N データシートの表示（PDF） - NXP Semiconductors.
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74LV595N Datasheet PDF : 20 Pages
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NXP Semiconductors
74LV595
8-bit serial-in/serial-out or parallel-out shift register; 3-state
Table 7. Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 13.
Symbol Parameter
Conditions
−40 °C to +85 °C
Min Typ[1] Max
tW
pulse width
SHCP, HIGH or LOW;
see Figure 8
VCC = 2.0 V
VCC = 2.7 V
VCC = 3.0 V to 3.6 V
STCP, HIGH or LOW;
see Figure 9
34
10
-
25
8
-
[3] 20
6
-
VCC = 2.0 V
VCC = 2.7 V
VCC = 3.0 V to 3.6 V
MR LOW; see Figure 11
34
7
-
25
5
-
[3] 20
4
-
tsu
set-up time
VCC = 2.0 V
34
10
-
VCC = 2.7 V
VCC = 3.0 V to 3.6 V
25
8
-
[3] 20
6
-
DS to SHCP; see Figure 10
VCC = 1.2 V
-
40
-
VCC = 2.0 V
26
14
-
VCC = 2.7 V
VCC = 3.0 V to 3.6 V
19
10
-
[3] 15
8
-
SHCP to STCP; see Figure 9
VCC = 1.2 V
-
40
-
VCC = 2.0 V
26
14
-
VCC = 2.7 V
19
10
-
VCC = 3.0 V to 3.6 V
[3] 15
8
-
th
hold time
DS to SHCP; see Figure 10
VCC = 1.2 V
-
−10.0
-
VCC = 2.0 V
5.0 −4.0
-
VCC = 2.7 V
5.0 −3.0
-
VCC = 3.0 V to 3.6 V
5.0 −2.0
-
trec
recovery time
MR to SHCP; see Figure 11
VCC = 1.2 V
-
−35
-
VCC = 2.0 V
5.0 −12.0
-
VCC = 2.7 V
5.0 −9.0
-
VCC = 3.0 V to 3.6 V
[3] 5.0
−7.0
-
−40 °C to +125 °C Unit
Min
Max
41
-
ns
30
-
ns
24
-
ns
41
-
ns
30
-
ns
24
-
ns
41
-
ns
30
-
ns
24
-
ns
-
-
ns
31
-
ns
23
-
ns
18
-
ns
-
-
ns
31
-
ns
23
-
ns
18
-
ns
-
-
ns
5.0
-
ns
5.0
-
ns
5.0
-
ns
-
-
ns
5.0
-
ns
5.0
-
ns
5.0
-
ns
74LV595_3
Product data sheet
Rev. 03 — 21 April 2009
© NXP B.V. 2009. All rights reserved.
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