74LVC08AD データシートの表示（PDF） - NXP Semiconductors.

部品番号

コンポーネント説明

メーカー

74LVC08AD

Quad 2-input AND gate

NXP Semiconductors. 

Nexperia

4. Functional diagram

74LVC08A

Quad 2-input AND gate







 $

 %

 $

 %

 $

 %

 $

 %

< 

< 

< 

< 

PQD

Fig 1. Logic symbol



















PQD

Fig 2. IEC logic symbol

5. Pinning information

5.1 Pinning

$

<

%

PQD

Fig 3. Logic diagram for one gate

74LVC08A

1A 1

1B 2

1Y 3

2A 4

2B 5

2Y 6

GND 7

14 VCC

13 4B

12 4A

11 4Y

10 3B

9 3A

8 3Y

001aac945

Fig 4. Pin configuration SO14 and (T)SSOP14

terminal 1

index area

74LVC08A

1B 2

1Y 3

2A 4

2B 5

2Y 6

GND(1)

13 4B

12 4A

11 4Y

10 3B

9 3A

001aac946

Transparent top view

(1) This is not a supply pin. The substrate is attached to this

pad using conductive die attach material. There is no

electrical or mechanical requirement to solder this pad.

However, if it is soldered, the solder land should remain

floating or be connected to GND.

Fig 5. Pin configuration DHVQFN14

74LVC08A

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 7 — 19 April 2016

© Nexperia B.V. 2017. All rights reserved

2 of 15

Share Link: